failoverR.diff: Revert my failover change since Kconfig only supports fallback.

kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 302 insertions, 28 deletions

diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb
index d6d5279203..9c6446eda6 100644
--- a/src/mainboard/tyan/s2895/Config.lb
+++ b/src/mainboard/tyan/s2895/Config.lb
@@ -29,25 +29,10 @@ if CONFIG_HAVE_ACPI_TABLES
 end
 
 if CONFIG_USE_INIT
-if CONFIG_USE_FAILOVER_IMAGE
-	makerule ./auto.o
-		depends "$(CONFIG_MAINBOARD)/failover.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/failover.c -o $@"
-	end
-else
 	makerule ./auto.o
 		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
 		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 	end
-end
-else #CONFIG_USE_INIT
-if CONFIG_USE_FAILOVER_IMAGE
-	makerule ./auto.inc
-		depends "$(CONFIG_MAINBOARD)/failover.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/failover.c -o $@"
-		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
 else
 	makerule ./auto.inc
 		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -56,32 +41,51 @@ else
 		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 	end
 end
-end #CONFIG_USE_INIT
 
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
+if CONFIG_HAVE_FAILOVER_BOOT
+	if CONFIG_USE_FAILOVER_IMAGE
+		mainboardinit cpu/x86/16bit/entry16.inc
+		ldscript /cpu/x86/16bit/entry16.lds
+	end
+else
+	if CONFIG_USE_FALLBACK_IMAGE
+		mainboardinit cpu/x86/16bit/entry16.inc
+		ldscript /cpu/x86/16bit/entry16.lds
+	end
 end
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
 	if CONFIG_USE_INIT
 		ldscript /cpu/x86/32bit/entry32.lds
+	end
+
+	if CONFIG_USE_INIT
 		ldscript /cpu/amd/car/cache_as_ram.lds
 	end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if CONFIG_USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
+    else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+    end
 else
+    if CONFIG_USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+    else
 	mainboardinit cpu/x86/32bit/reset32.inc
 	ldscript /cpu/x86/32bit/reset32.lds
+    end
 end
 
 ##
@@ -93,9 +97,16 @@ ldscript /southbridge/nvidia/ck804/id.lds
 ##
 ## ROMSTRAP table for CK804
 ##
-if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit southbridge/nvidia/ck804/romstrap.inc
-	ldscript /southbridge/nvidia/ck804/romstrap.lds
+if CONFIG_HAVE_FAILOVER_BOOT
+	if CONFIG_USE_FAILOVER_IMAGE
+		mainboardinit southbridge/nvidia/ck804/romstrap.inc
+		ldscript /southbridge/nvidia/ck804/romstrap.lds
+	end
+else
+	if CONFIG_USE_FALLBACK_IMAGE
+		mainboardinit southbridge/nvidia/ck804/romstrap.inc
+		ldscript /southbridge/nvidia/ck804/romstrap.lds
+	end
 end
 
 ##
@@ -108,8 +119,14 @@ end
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if CONFIG_USE_FAILOVER_IMAGE
-	ldscript /arch/i386/lib/failover_failover.lds
+if CONFIG_HAVE_FAILOVER_BOOT
+	if CONFIG_USE_FAILOVER_IMAGE
+			ldscript /arch/i386/lib/failover_failover.lds
+	end
+else
+	if CONFIG_USE_FALLBACK_IMAGE
+			ldscript /arch/i386/lib/failover.lds
+	end
 end
 
 ##
diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig
new file mode 100644
index 0000000000..3528b8c71a
--- /dev/null
+++ b/src/mainboard/tyan/s2895/Kconfig
@@ -0,0 +1,142 @@
+config BOARD_TYAN_S2895
+	bool "Tyan Thunder K8WE S2895"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_940
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_NVIDIA_CK804
+	select SOUTHBRIDGE_AMD_AMD8131
+	select SUPERIO_SMSC_LPC47B397
+	select PIRQ_TABLE
+
+config MAINBOARD_DIR
+	string
+	default tyan/s2895
+	depends on BOARD_TYAN_S2895
+
+config APIC_ID_OFFSET
+	hex
+	default 8
+	depends on BOARD_TYAN_S2895
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 2
+	depends on BOARD_TYAN_S2895
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_TYAN_S2895
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_TYAN_S2895
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "s2895"
+	depends on BOARD_TYAN_S2895
+
+config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x2895
+	depends on BOARD_TYAN_S2895
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_TYAN_S2895
+
+config MEM_TRAIN_SEQ
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config HAVE_FAILOVER_BOOT
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config MAX_CPUS
+	int
+	default 4
+	depends on BOARD_TYAN_S2895
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+	depends on BOARD_TYAN_S2895
+
+config MEM_TRAIN_SEQ
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config AP_CODE_IN_CAR
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0
+	depends on BOARD_TYAN_S2895
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x20
+	depends on BOARD_TYAN_S2895
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config SERIAL_CPU_INIT
+	bool
+	default y
+	depends on BOARD_TYAN_S2895
+
+config AP_CODE_IN_CAR
+	bool
+	default y
+	depends on BOARD_TYAN_S2895
+
+config WAIT_BEFORE_CPUS_INIT
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 2
+	depends on BOARD_TYAN_S2895
+
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	bool
+	default n
+	depends on BOARD_TYAN_S2895
+
+config HAVE_ACPI_TABLES
+	bool "Generate ACPI tables"
+	default y
+	depends on BOARD_TYAN_S2895
+
diff --git a/src/mainboard/tyan/s2895/Makefile.inc b/src/mainboard/tyan/s2895/Makefile.inc
new file mode 100644
index 0000000000..88582f5329
--- /dev/null
+++ b/src/mainboard/tyan/s2895/Makefile.inc
@@ -0,0 +1 @@
+include $(src)/mainboard/tyan/Makefile.s289x.inc
diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
index 080d27b32c..2da764f24e 100644
--- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
@@ -1,3 +1,4 @@
+#define ASSEMBLY 1
 #define __ROMCC__
 
 #define K8_ALLOCATE_IO_RANGE 1
@@ -20,12 +21,11 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#define post_code(x) outb(x, 0x80)
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-
 #include <cpu/amd/model_fxx_rev.h>
 
 #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -34,6 +34,8 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
+#endif
+
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
@@ -42,6 +44,8 @@
 
 #define SUPERIO_GPIO_IO_BASE 0x400
 
+#if CONFIG_USE_FAILOVER_IMAGE==0
+
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -114,8 +118,117 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/init_cpus.c"
 
+#endif
+
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
+
+#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+static void sio_setup(void)
+{
+
+	unsigned value;
+	uint32_t dword;
+	uint8_t byte;
+
+	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
+
+	byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
+	byte |= 0x20;
+	pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
+
+	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
+	dword |= (1<<29)|(1<<0);
+	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+
+	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
+	dword |= (1<<16);
+	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
+
+	lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
+	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
+	value &= 0xbf;
+	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
+
+}
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	unsigned last_boot_normal_x = last_boot_normal();
+
+	/* Is this a cpu only reset? or Is this a secondary cpu? */
+	if ((cpu_init_detectedx) || (!boot_cpu())) {
+	if (last_boot_normal_x) {
+	goto normal_image;
+	} else {
+	goto fallback_image;
+	}
+	}
+
+	/* Nothing special needs to be done to find bus 0 */
+	/* Allow the HT devices to be found */
+
+	enumerate_ht_chain();
+
+	sio_setup();
+
+	/* Setup the ck804 */
+	ck804_enable_rom();
+
+	/* Is this a deliberate reset by the bios */
+//	post_code(0x22);
+	if (bios_reset_detected() && last_boot_normal_x) {
+	goto normal_image;
+	}
+	/* This is the primary cpu how should I boot? */
+	else if (do_normal_boot()) {
+	goto normal_image;
+	}
+	else {
+	goto fallback_image;
+	}
+ normal_image:
+//	post_code(0x23);
+	__asm__ volatile ("jmp __normal_image"
+	: /* outputs */
+	: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
+	);
+
+ fallback_image:
+//	post_code(0x25);
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+	__asm__ volatile ("jmp __fallback_image"
+	: /* outputs */
+	: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+	)
+#endif
+	;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+	#if CONFIG_USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);
+	#else
+	real_main(bist, cpu_init_detectedx);
+	#endif
+#else
+	#if CONFIG_USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);
+	#endif
+	real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if CONFIG_USE_FAILOVER_IMAGE==0
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
 	static const uint16_t spd_addr [] = {
 		(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 		(0xa<<3)|1, (0xa<<3)|3, 0, 0,
@@ -135,7 +248,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		bsp_apicid = init_cpus(cpu_init_detectedx);
 	}
 
-	post_code(0x32);
+//	post_code(0x32);
 
 	lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
@@ -197,3 +310,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
+#endif