Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34

Creator:  Yinghai Lu <yhlu@tyan.com>

AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 49 insertions, 3 deletions

diff --git a/src/mainboard/tyan/s2895/auto.c b/src/mainboard/tyan/s2895/auto.c
index 209f284d58..b6f121e6e8 100644
--- a/src/mainboard/tyan/s2895/auto.c
+++ b/src/mainboard/tyan/s2895/auto.c
@@ -105,6 +105,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 /* tyan does not want the default */
 #include "resourcemap.c"
 
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#include "cpu/amd/dualcore/dualcore.c"
+#else
+#include "cpu/amd/model_fxx/node_id.c"
+#endif
+
 #define FIRST_CPU  1
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@@ -113,6 +120,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define CK804B_BUSN 0xc
 #define CK804_USE_NIC 1
 #define CK804_USE_ACI 1
+#include "southbridge/nvidia/ck804/ck804_early_setup.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 
 //set GPIO to input mode
@@ -155,26 +163,57 @@ static void main(unsigned long bist)
 	};
 
         int needs_reset;
+#if CONFIG_LOGICAL_CPUS==1
+        struct node_core_id id;
+#else
         unsigned nodeid;
+#endif
 
         if (bist == 0) {
                 /* Skip this if there was a built in self test failure */
                 amd_early_mtrr_init();
 
-                nodeid = lapicid();;
+#if CONFIG_LOGICAL_CPUS==1
+                set_apicid_cpuid_lo();
+                
+                id = get_node_core_id_x(); // that is initid
+        #if ENABLE_APIC_EXT_ID == 1
+                if(id.coreid == 0) {
+                        enable_apic_ext_id(id.nodeid);
+                }
+        #endif
+#else           
+                nodeid = get_node_id();
         #if ENABLE_APIC_EXT_ID == 1
                 enable_apic_ext_id(nodeid);
         #endif
+#endif
 
                 enable_lapic();
                 init_timer();
 
 
+#if CONFIG_LOGICAL_CPUS==1
+        #if ENABLE_APIC_EXT_ID == 1
+            #if LIFT_BSP_APIC_ID == 0
+                if( id.nodeid != 0 ) 
+            #endif
+                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
+        #endif
+
+                if(id.coreid == 0) {
+                        if (cpu_init_detected(id.nodeid)) {
+                                asm volatile ("jmp __cpu_reset");
+                        }
+                        distinguish_cpu_resets(id.nodeid);
+                }
+
+#else
         #if ENABLE_APIC_EXT_ID == 1
             #if LIFT_BSP_APIC_ID == 0
                 if(nodeid != 0)
             #endif
-                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
+                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); 
 
         #endif
 
@@ -182,11 +221,15 @@ static void main(unsigned long bist)
                         asm volatile ("jmp __cpu_reset");
                 }
                 distinguish_cpu_resets(nodeid);
+#endif
 
 
                 if (!boot_cpu()
+#if CONFIG_LOGICAL_CPUS==1 
+                        || (id.coreid != 0)
+#endif
                 ) {
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
+                        stop_this_cpu(); 
                 }
         }
 
@@ -203,6 +246,9 @@ static void main(unsigned long bist)
         setup_s2895_resource_map();
 
 	needs_reset = setup_coherent_ht_domain();
+#if CONFIG_LOGICAL_CPUS==1
+        start_other_cores();
+#endif
 
         needs_reset |= ht_setup_chains_x();