diff options
author | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 23:57:49 +0000 |
---|---|---|
committer | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 23:57:49 +0000 |
commit | 6d74d76de46e733fa4866f47b58be60feb472f1f (patch) | |
tree | 16f31f8d51e6eaa021bc26a47d6c8d92568c5fb3 /src/mainboard/tyan/s2892 | |
parent | d95465d08f5be0ec46fe3b1f801b98f7c5a43f81 (diff) |
get_bus_cong using sysconf instead
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2892')
-rw-r--r-- | src/mainboard/tyan/s2892/Config.lb | 3 | ||||
-rw-r--r-- | src/mainboard/tyan/s2892/Options.lb | 17 | ||||
-rw-r--r-- | src/mainboard/tyan/s2892/auto.c | 2 | ||||
-rw-r--r-- | src/mainboard/tyan/s2892/cache_as_ram_auto.c | 103 | ||||
-rw-r--r-- | src/mainboard/tyan/s2892/cmos.layout | 8 | ||||
-rw-r--r-- | src/mainboard/tyan/s2892/get_bus_conf.c | 41 | ||||
-rw-r--r-- | src/mainboard/tyan/s2892/irq_tables.c | 6 | ||||
-rw-r--r-- | src/mainboard/tyan/s2892/mptable.c | 9 | ||||
-rw-r--r-- | src/mainboard/tyan/s2892/resourcemap.c | 4 |
9 files changed, 114 insertions, 79 deletions
diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb index 6fa8e5d44a..dcb0c45abf 100644 --- a/src/mainboard/tyan/s2892/Config.lb +++ b/src/mainboard/tyan/s2892/Config.lb @@ -313,8 +313,7 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - # register "rom_address" = "0xfff80000" #for 512K - register "rom_address" = "0xfff00000" #for 1M + register "rom_address" = "0xfff80000" end chip drivers/pci/onboard device pci 8.0 on end diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index 30e6d617c2..92ebe2e738 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -54,7 +54,6 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -66,12 +65,14 @@ uses HT_CHAIN_END_UNITID_BASE uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_LB_MEM_TOPK + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -#default ROM_SIZE=524288 +default ROM_SIZE=524288 #1M bytes -default ROM_SIZE=1048576 +#default ROM_SIZE=1048576 ## @@ -128,12 +129,6 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -#1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 - -#Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 - ##HT Unit ID offset, default is 1, the typical one default HT_CHAIN_UNITID_BASE=0x0 @@ -146,6 +141,9 @@ default SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#1G memory hole +default HW_MEM_HOLE_SIZEK=0x100000 + #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -161,6 +159,7 @@ default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 + ## ## Build code to setup a generic IOAPIC ## diff --git a/src/mainboard/tyan/s2892/auto.c b/src/mainboard/tyan/s2892/auto.c index 07d7b5ec8b..1d19ecfafc 100644 --- a/src/mainboard/tyan/s2892/auto.c +++ b/src/mainboard/tyan/s2892/auto.c @@ -12,7 +12,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/cpu_rev.c" #define K8_HT_FREQ_1G_SUPPORT 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c index 5dd43e8bbc..4b63ffed4e 100644 --- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c @@ -13,6 +13,17 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" @@ -54,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -98,7 +109,7 @@ static void sio_setup(void) uint32_t dword; uint8_t byte; - byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); @@ -106,7 +117,6 @@ static void sio_setup(void) dword |= (1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); - } void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -132,6 +142,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ck804_enable_rom(); /* Is this a deliberate reset by the bios */ +// post_code(0x22); if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } @@ -143,12 +154,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) goto fallback_image; } normal_image: +// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ ); fallback_image: +// post_code(0x25); ; } #endif @@ -167,46 +180,42 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const struct mem_controller cpu[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, - }, + + static const uint16_t spd_addr [] = { + (0xa<<3)|0, (0xa<<3)|2, 0, 0, + (0xa<<3)|1, (0xa<<3)|3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, - }, + (0xa<<3)|4, (0xa<<3)|6, 0, 0, + (0xa<<3)|5, (0xa<<3)|7, 0, 0, #endif - }; + }; - unsigned bsp_apicid = 0; int needs_reset; + unsigned bsp_apicid = 0; + + struct mem_controller ctrl[8]; + unsigned nodes; if (bist == 0) { init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); +// post_code(0x32); + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); setup_s2892_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif - needs_reset = setup_coherent_ht_domain(); + needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 @@ -219,15 +228,35 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ck804_early_setup_x(); - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + allow_all_aps_stop(bsp_apicid); + + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); + + enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif +#if 0 + dump_smbus_registers(); +#endif - enable_smbus(); + memreset_setup(); + sdram_initialize(nodes, ctrl); - memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); +#if 0 + print_pci_devices(); +#endif + +#if 0 + dump_pci_devices(); +#endif - post_cache_as_ram(); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2892/cmos.layout b/src/mainboard/tyan/s2892/cmos.layout index 5eb88b9a5a..c1f3d75316 100644 --- a/src/mainboard/tyan/s2892/cmos.layout +++ b/src/mainboard/tyan/s2892/cmos.layout @@ -78,10 +78,10 @@ enumerations 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz 9 0 off 9 1 87.5% 9 2 75.0% diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 6086aa5ff5..2e8a5cd337 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -7,6 +7,7 @@ #include <cpu/amd/dualcore.h> #endif +#include <cpu/amd/amdk8_sysconf.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default @@ -24,8 +25,7 @@ unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned sblk; -unsigned pci1234[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -37,9 +37,7 @@ unsigned pci1234[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hc_possible_num; -unsigned sbdn; -unsigned hcdn[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -61,23 +59,29 @@ void get_bus_conf(void) { unsigned apicid_base; + unsigned sbdn; device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done==1) return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); - - get_sblk_pci1234(); + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i<sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); - sbdn = (hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sbdn = sysconf.sbdn; - sbdn3 = (hcdn[1] & 0xff); // first byte of second chain + sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain -// bus_ck804_0 = node_link_to_bus(0, sblk); - bus_ck804_0 = (pci1234[0] >> 16) & 0xff; + bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; /* CK804 */ @@ -145,16 +149,15 @@ void get_bus_conf(void) dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); if (dev) { bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_0++; - bus_isa = bus_8131_0; // incase only one installed + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; } else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - } - bus_8131_0 = (pci1234[1] >> 16) & 0xff; + bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; + /* 8131-1 */ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { diff --git a/src/mainboard/tyan/s2892/irq_tables.c b/src/mainboard/tyan/s2892/irq_tables.c index b4d61aaaea..a1b2b2ed37 100644 --- a/src/mainboard/tyan/s2892/irq_tables.c +++ b/src/mainboard/tyan/s2892/irq_tables.c @@ -10,6 +10,8 @@ #include <stdint.h> #include <arch/pirq_routing.h> +#include <cpu/amd/amdk8_sysconf.h> + static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) @@ -39,8 +41,6 @@ extern unsigned char bus_8131_0;//7 extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_2;//9 -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern void get_bus_conf(void); @@ -52,11 +52,13 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_info *pirq_info; unsigned slot_num; uint8_t *v; + unsigned sbdn; uint8_t sum=0; int i; get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + sbdn = sysconf.sbdn; /* Align the table to be 16 byte aligned. */ addr += 15; diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index e0f16d8921..4828453741 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -4,6 +4,8 @@ #include <string.h> #include <stdint.h> +#include <cpu/amd/amdk8_sysconf.h> + extern unsigned char bus_isa; extern unsigned char bus_ck804_0; //1 extern unsigned char bus_ck804_1; //2 @@ -18,8 +20,6 @@ extern unsigned apicid_ck804; extern unsigned apicid_8131_1; extern unsigned apicid_8131_2; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; @@ -29,6 +29,7 @@ void *smp_write_config_table(void *v) static const char oem[8] = "TYAN "; static const char productid[12] = "S2892 "; struct mp_config_table *mc; + unsigned sbdn; unsigned char bus_num; int i; @@ -53,6 +54,7 @@ void *smp_write_config_table(void *v) smp_write_processors(mc); get_bus_conf(); + sbdn = sysconf.sbdn; /*Bus: Bus ID Type*/ /* define bus and isa numbers */ @@ -74,11 +76,12 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } + /* Initialize interrupt mapping*/ + dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; - pci_write_config32(dev, 0x80, dword); dword = 0x0000007d; diff --git a/src/mainboard/tyan/s2892/resourcemap.c b/src/mainboard/tyan/s2892/resourcemap.c index 5801264a16..b7d72db90e 100644 --- a/src/mainboard/tyan/s2892/resourcemap.c +++ b/src/mainboard/tyan/s2892/resourcemap.c @@ -258,8 +258,8 @@ static void setup_s2892_resource_map(void) * This field defines the highest bus number in configuration region i */ #if 1 -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, #endif |