Applying 11_26_car_tyan.diff from Yinghai Lu.

NOTE: This will break the tree so it can be fixed up later



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 46 insertions, 196 deletions

diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb
index 504f12d270..f4a32837e1 100644
--- a/src/mainboard/tyan/s2892/Config.lb
+++ b/src/mainboard/tyan/s2892/Config.lb
@@ -97,9 +97,12 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
 
 if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb
index 5d860bddae..ede4fe9708 100644
--- a/src/mainboard/tyan/s2892/Options.lb
+++ b/src/mainboard/tyan/s2892/Options.lb
@@ -53,7 +53,7 @@ uses CONFIG_GDB_STUB
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses CK804_DEVN_BASE
 
@@ -73,7 +73,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ###
 ### Build options
@@ -123,7 +125,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #CK804 setting
 
@@ -139,10 +141,10 @@ default CONFIG_PCI_ROM_RUN=1
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
 
 
 ##
diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c
index 5158bccf55..27d87ecceb 100644
--- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c
@@ -14,7 +14,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -85,14 +84,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
+#include "cpu/amd/dualcore/dualcore.c"
 
 #define CK804_NUM 1
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@ -107,6 +100,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
@@ -129,38 +127,13 @@ static void sio_setup(void)
 
 
 }
-void real_main(unsigned long bist);
-
-void amd64_main(unsigned long bist)
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
+        unsigned last_boot_normal_x = last_boot_normal();
 
-#if CONFIG_LOGICAL_CPUS==1
-        id = get_node_core_id_x();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid() & 0xf;
-        nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -178,7 +151,7 @@ void amd64_main(unsigned long bist)
         ck804_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -191,27 +164,29 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
-                );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
+                : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
                 );
-#endif
-
+ 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
 		{
 			.node_id = 0,
 			.f0 = PCI_DEV(0, 0x18, 0),
@@ -221,8 +196,7 @@ void amd64_main(unsigned long bist)
 			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 		},
-#endif
-#if SECOND_CPU
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
 		{
 			.node_id = 1,
 			.f0 = PCI_DEV(0, 0x19, 0),
@@ -239,56 +213,9 @@ void amd64_main(unsigned long bist)
 	unsigned cpu_reset = 0;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
-                struct node_core_id id;
-#else
-                unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-                id = get_node_core_id_x(); // that is initid
-#else
-                nodeid = get_node_id();
-#endif
-
-                enable_lapic();
-//                init_timer();
-
-#if CONFIG_LOGICAL_CPUS==1
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-                                cpu_reset = 1;
-                                goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-                if (cpu_init_detected(nodeid)) {
-                                cpu_reset = 1;
-                                goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-                        // We need stop the CACHE as RAM for this CPU too
-                        #include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
-
+		init_cpus(cpu_init_detectedx);
         }
 
-	init_timer(); // only do it it first CPU
-
-	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
@@ -301,8 +228,10 @@ void amd64_main(unsigned long bist)
 	needs_reset = setup_coherent_ht_domain();
 	
 #if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
+
         needs_reset |= ht_setup_chains_x();
 
         needs_reset |= ck804_early_setup_x();
@@ -317,89 +246,5 @@ void amd64_main(unsigned long bist)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-
-#if 1
-        {
-        	/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-	        unsigned v_esp;
-	        __asm__ volatile (
-        	        "movl   %%esp, %0\n\t"
-	                : "=a" (v_esp)
-	        );
-#if CONFIG_USE_INIT
-	        printk_debug("v_esp=%08x\r\n", v_esp);
-#else
-	        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif
-        }
-
-#endif
-#if 1
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		/* We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("Use Ram as Stack now - done\r\n");	
-		} else 
-		{	
-			print_debug("Use Ram as Stack now - \r\n");
-		}
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-	
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
-
+	post_cache_as_ram(cpu_reset);
 }