diff options
author | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 23:57:49 +0000 |
---|---|---|
committer | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 23:57:49 +0000 |
commit | 6d74d76de46e733fa4866f47b58be60feb472f1f (patch) | |
tree | 16f31f8d51e6eaa021bc26a47d6c8d92568c5fb3 /src/mainboard/tyan/s2885 | |
parent | d95465d08f5be0ec46fe3b1f801b98f7c5a43f81 (diff) |
get_bus_cong using sysconf instead
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2885')
-rw-r--r-- | src/mainboard/tyan/s2885/Options.lb | 19 | ||||
-rw-r--r-- | src/mainboard/tyan/s2885/auto.c | 2 | ||||
-rw-r--r-- | src/mainboard/tyan/s2885/cache_as_ram_auto.c | 31 | ||||
-rw-r--r-- | src/mainboard/tyan/s2885/cmos.layout | 8 | ||||
-rw-r--r-- | src/mainboard/tyan/s2885/get_bus_conf.c | 46 | ||||
-rw-r--r-- | src/mainboard/tyan/s2885/irq_tables.c | 8 | ||||
-rw-r--r-- | src/mainboard/tyan/s2885/mptable.c | 8 |
7 files changed, 86 insertions, 36 deletions
diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb index 5ca7df6a34..9828e61c1e 100644 --- a/src/mainboard/tyan/s2885/Options.lb +++ b/src/mainboard/tyan/s2885/Options.lb @@ -63,6 +63,13 @@ uses ENABLE_APIC_EXT_ID uses APIC_ID_OFFSET uses LIFT_BSP_APIC_ID +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_LB_MEM_TOPK + ### ### Build options ### @@ -125,6 +132,18 @@ default CONFIG_LOGICAL_CPUS=1 #CHIP_NAME ? default CONFIG_CHIP_NAME=1 +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0a + +##real SB Unit ID, default is 0x20, mean dont touch it at last +default HT_CHAIN_END_UNITID_BASE=0x06 + +#make the SB HT chain on bus 0, default is not (0) +default SB_HT_CHAIN_ON_BUS0=2 + +##only offset for SB chain?, default is yes(1) +#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000 diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c index 1e52e4e774..f4f30737ab 100644 --- a/src/mainboard/tyan/s2885/auto.c +++ b/src/mainboard/tyan/s2885/auto.c @@ -19,7 +19,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/incoherent_ht.c" -#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/cpu_rev.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/tyan/s2885/cache_as_ram_auto.c b/src/mainboard/tyan/s2885/cache_as_ram_auto.c index 13b66d8dc5..5d43c71f9a 100644 --- a/src/mainboard/tyan/s2885/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2885/cache_as_ram_auto.c @@ -13,7 +13,19 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + #include <cpu/amd/model_fxx_rev.h> + #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -68,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -113,9 +125,11 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); + /* Setup the ck804 */ amd8111_enable_rom(); /* Is this a deliberate reset by the bios */ +// post_code(0x22); if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } @@ -127,12 +141,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) goto fallback_image; } normal_image: +// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ ); fallback_image: +// post_code(0x25); ; } #endif @@ -170,15 +186,22 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } +// post_code(0x32); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); + /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_s2885_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif needs_reset = setup_coherent_ht_domain(); @@ -188,7 +211,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + needs_reset |= ht_setup_chains_x(); if (needs_reset) { @@ -208,6 +231,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); +#if 0 + dump_pci_devices(); +#endif + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2885/cmos.layout b/src/mainboard/tyan/s2885/cmos.layout index 5eb88b9a5a..c1f3d75316 100644 --- a/src/mainboard/tyan/s2885/cmos.layout +++ b/src/mainboard/tyan/s2885/cmos.layout @@ -78,10 +78,10 @@ enumerations 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz 9 0 off 9 1 87.5% 9 2 75.0% diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index 5e8e0bd347..68ed3d2e87 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -7,6 +7,7 @@ #include <cpu/amd/dualcore.h> #endif +#include <cpu/amd/amdk8_sysconf.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default @@ -22,8 +23,7 @@ unsigned apicid_8111 ; unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned sblk; -unsigned pci1234[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -35,9 +35,7 @@ unsigned pci1234[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hc_possible_num; -unsigned sbdn; -unsigned hcdn[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -61,24 +59,29 @@ void get_bus_conf(void) unsigned apicid_base; device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done==1) return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); - - get_sblk_pci1234(); + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i<sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); - sbdn = (hcdn[0] >> 8) & 0xff; - sbdn3 = hcdn[0] & 0xff; - sbdn5 = hcdn[1] & 0xff; + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; + sbdn3 = sysconf.hcdn[0] & 0xff; + sbdn5 = sysconf.hcdn[1] & 0xff; - bus_8131_0 = (pci1234[0] >> 16) & 0xff; + bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; bus_8111_0 = bus_8131_0; /* 8111 */ - dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0)); + dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); #if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE @@ -95,11 +98,6 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; -// printk_debug("bus_isa=%d\n",bus_isa); -#endif } else { printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); @@ -109,6 +107,12 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; +// printk_debug("bus_isa=%d\n",bus_isa); +#endif + } else { printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); @@ -116,7 +120,7 @@ void get_bus_conf(void) /* HT chain 1 */ // it is on node0, so it must be there - bus_8151_0 = (pci1234[1] >> 16) & 0xff; + bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff; /* 8151 */ dev = dev_find_slot(bus_8151_0, PCI_DEVFN(sbdn5+1, 0)); diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c index 59c3704c83..4fc12a04ac 100644 --- a/src/mainboard/tyan/s2885/irq_tables.c +++ b/src/mainboard/tyan/s2885/irq_tables.c @@ -10,6 +10,8 @@ #include <stdint.h> #include <arch/pirq_routing.h> +#include <cpu/amd/amdk8_sysconf.h> + static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) @@ -36,8 +38,6 @@ extern unsigned char bus_8111_1; extern unsigned char bus_8151_0; extern unsigned char bus_8151_1; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern unsigned sbdn5; @@ -70,7 +70,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->version = PIRQ_VERSION; pirq->rtr_bus = bus_8111_0; - pirq->rtr_devfn = ((sbdn+1)<<3)|0; + pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; @@ -84,7 +84,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge // write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index 83cbaf0e18..b126d2f60d 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -4,6 +4,8 @@ #include <string.h> #include <stdint.h> +#include <cpu/amd/amdk8_sysconf.h> + extern unsigned char bus_isa; extern unsigned char bus_8131_0; extern unsigned char bus_8131_1; @@ -16,8 +18,6 @@ extern unsigned apicid_8111; extern unsigned apicid_8131_1; extern unsigned apicid_8131_2; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern unsigned sbdn5; @@ -99,9 +99,9 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); //??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13); //Onboard AMD AC97 Audio - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11); // Onboard AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); |