Major merge of YhLu's code from 2004/04/20: add s2875, various other updates,

cleanups. Drop "driver" code from mainboard directories and use them from the
driver directory instead


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 144 insertions, 129 deletions

diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c
index 2915886cc9..712ff731d1 100644
--- a/src/mainboard/tyan/s2885/auto.c
+++ b/src/mainboard/tyan/s2885/auto.c
@@ -1,4 +1,5 @@
-#define ASSEMBLY 1 
+#define ASSEMBLY 1
+ 
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -41,21 +42,22 @@ static void soft_reset(void)
 
 static void memreset_setup(void)
 {
-	if (is_cpu_pre_c0()) {
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-	} else {
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-	}
+   if (is_cpu_pre_c0()) {
+        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
+   }
+   else {
+        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
+   }
+        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-		udelay(90);
-	}
+   if (is_cpu_pre_c0()) {
+        udelay(800);
+        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+        udelay(90);
+   }
 }
 
 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
@@ -82,20 +84,21 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 	 *     [3] Route to Link 2
 	 */
 
-	uint32_t ret = 0x00010101; /* default row entry */
+	uint32_t ret=0x00010101; /* default row entry */
 
 	static const unsigned int rows_2p[2][2] = {
 		{ 0x00050101, 0x00010404 },
 		{ 0x00010404, 0x00050101 }
 	};
 
-	if (maxnodes > 2) {
+	if(maxnodes>2) {
 		print_debug("this mainboard is only designed for 2 cpus\r\n");
-		maxnodes = 2;
+		maxnodes=2;
 	}
 
-	if (!(node >= maxnodes || row >= maxnodes)) {
-		ret = rows_2p[node][row];
+
+	if (!(node>=maxnodes || row>=maxnodes)) {
+		ret=rows_2p[node][row];
 	}
 
 	return ret;
@@ -147,10 +150,10 @@ static void main(void)
 #endif
 	};
 
+#if 1
         static const struct ht_chain ht_c[] = {
                 {
                         .udev = PCI_DEV(0, 0x18, 0),
-			/* LDT2 */
                         .upos = 0xc0,
                         .devreg = 0xe0,
                 }, 
@@ -160,27 +163,28 @@ static void main(void)
                         .devreg = 0xe4,
                 },
         };
-        int needs_reset;
+#endif
 
+        int needs_reset;
         enable_lapic();
         init_timer();
-
         if (cpu_init_detected()) {
                 asm("jmp __cpu_reset");
         }
-
         distinguish_cpu_resets();
         if (!boot_cpu()) {
                 stop_this_cpu();
         }
-
         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
-
         setup_s2885_resource_map();
         needs_reset = setup_coherent_ht_domain();
+#if 0
+        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
+#else
         needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
+#endif
         if (needs_reset) {
                 print_info("ht reset -\r\n");
                 soft_reset();
@@ -189,22 +193,20 @@ static void main(void)
         dump_pci_devices();
 #endif
 
-
 #if 0
 	print_pci_devices();
 #endif
-
 	enable_smbus();
-
 #if 0
 	dump_spd_registers(&cpu[0]);
 #endif
-
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
 #if 0
 	dump_pci_devices();
+#endif
+#if 0
 	dump_pci_device(PCI_DEV(0, 0x18, 1));
 #endif
 
@@ -216,7 +218,11 @@ static void main(void)
 	print_debug_hex32(msr.hi);
 	print_debug_hex32(msr.lo);
 	print_debug("\r\n");
+#endif
+/*
+#if  0
 	ram_check(0x00000000, msr.lo+(msr.hi<<32));
+#else 
 #if TOTAL_CPUS < 2
 	// Check 16MB of memory @ 0
 	ram_check(0x00000000, 0x00100000);
@@ -225,4 +231,5 @@ static void main(void)
 	ram_check(0x80000000, 0x80100000);
 #endif
 #endif
+*/
 }
diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c
index cc04c58716..b6a1c19460 100644
--- a/src/mainboard/tyan/s2885/irq_tables.c
+++ b/src/mainboard/tyan/s2885/irq_tables.c
@@ -20,16 +20,16 @@ const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0x35,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-		{0x03,(0x4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
-		{0x06,       0|0, {{0x0, 0x0000}, {0x0, 0x0000}, {0x0, 0x0000}, {0x4, 0xdef8}}, 0, 0},
-		{0x01,       0|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
-		{0x05,(0x3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
-		{0x05,(0x6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
-		{0x04,(0x8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
-		{0x04,(0x7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
-		{0x06,(0xa<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
-		{0x04,(0x9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
-		{0x06,(0xb<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-		{0x06,(0xc<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
+		{3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
+		{0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
+		{0x1,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
+		{0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
+		{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
+		{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
+		{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
+		{0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
+		{0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
+		{0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
+		{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
 	}
 };
diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c
index e142f1b6d7..b3e7c83cc9 100644
--- a/src/mainboard/tyan/s2885/mainboard.c
+++ b/src/mainboard/tyan/s2885/mainboard.c
@@ -87,10 +87,11 @@ static void amd8111_enable_rom(void)
         pci_write_config8(dev, 0x43, byte);
 }
 #endif
+#if 0
 static void onboard_scsi_fixup(void)
 {
         struct device *dev;
-#if 0 
+#if 1 
 	unsigned char i,j,k;
 
 	for(i=0;i<=6;i++) {
@@ -119,6 +120,7 @@ static void onboard_scsi_fixup(void)
 //	print_mem();
 //	amd8111_enable_rom();
 }
+#endif
 #if 0
 static void vga_fixup(void) {
         // we do this right here because:
@@ -153,8 +155,8 @@ enable(struct chip *chip, enum chip_pass pass)
 //		case CONF_PASS_PRE_PCI:
 //		case CONF_PASS_POST_PCI:		
                 case CONF_PASS_PRE_BOOT:
-			if (conf->fixup_scsi)
-        			onboard_scsi_fixup();
+//			if (conf->fixup_scsi)
+ //       			onboard_scsi_fixup();
 //			if (conf->fixup_vga)
 //				vga_fixup();
 			printk_debug("mainboard fixup pass %d done\r\n",
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index a3afe539fe..dd7cefcc85 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -6,19 +6,19 @@
 
 void *smp_write_config_table(void *v, unsigned long * processor_map)
 {
-	static const char sig[4] = "PCMP";
+        static const char sig[4] = "PCMP";
         static const char oem[8] = "TYAN    ";
         static const char productid[12] = "S2885       ";
         struct mp_config_table *mc;
 
         unsigned char bus_num;
         unsigned char bus_isa;
-        unsigned char bus_8111_0;
-        unsigned char bus_8111_1;
         unsigned char bus_8131_1;
         unsigned char bus_8131_2;
+        unsigned char bus_8111_1;
 	unsigned char bus_8151_1;
 
+
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
         memset(mc, 0, sizeof(*mc));
 
@@ -38,70 +38,81 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 
         smp_write_processors(mc, processor_map);
 
-	{
+       {
                 device_t dev;
 
                 /* 8111 */
                 dev = dev_find_slot(3, PCI_DEVFN(0x03,0));
                 if (dev) {
-                	bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
                         bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                         bus_isa++;
 			printk_debug("bus_isa=%d\n",bus_isa);
-                } else {
+                }
+                else {
                         printk_debug("ERROR - could not find PCI 3:03.0, using defaults\n");
+
                         bus_8111_1 = 6;
                         bus_isa = 7;
                 }
-
                 /* 8131-1 */
                 dev = dev_find_slot(3, PCI_DEVFN(0x01,0));
                 if (dev) {
                         bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                } else {
+
+                }
+                else {
                         printk_debug("ERROR - could not find PCI 3:01.0, using defaults\n");
+
                         bus_8131_1 = 4;
                 }
                 /* 8131-2 */
                 dev = dev_find_slot(3, PCI_DEVFN(0x02,0));
                 if (dev) {
                         bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                } else {
+
+                }
+                else {
                         printk_debug("ERROR - could not find PCI 3:02.0, using defaults\n");
+
                         bus_8131_2 = 5;
                 }
-		/* 8151 */
+	               /* 8151 */
                 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
                 if (dev) {
                         bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        printk_debug("bus_8151_1=%d\n",bus_8151_1);   
-                } else {
+                        printk_debug("bus_8151_1=%d\n",bus_8151_1);
+   
+                }
+                else {
                         printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+
                         bus_8151_1 = 2;
-		}
+                }
+  
+   
         }
 
-	/*Bus:		Bus ID	Type*/
-	/* define bus and isa numbers */
-        for (bus_num = 0; bus_num < bus_isa; bus_num++) {
+
+
+/*Bus:		Bus ID	Type*/
+       /* define bus and isa numbers */
+        for(bus_num = 0; bus_num < bus_isa; bus_num++) {
                 smp_write_bus(mc, bus_num, "PCI   ");
         }
         smp_write_bus(mc, bus_isa, "ISA   ");
 
-	/*I/O APICs:	APIC ID	Version	State		Address*/
+/*I/O APICs:	APIC ID	Version	State		Address*/
 	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
         {
                 struct pci_dev *dev;
                 uint32_t base;
-		/* 8131-1 APIC */
                 dev = dev_find_slot(3, PCI_DEVFN(0x1,1));
                 if (dev) {
                         base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
                         base &= PCI_BASE_ADDRESS_MEM_MASK;
                         smp_write_ioapic(mc, 3, 0x11, base);
                 }
-		/* 8131-2 APIC */
                 dev = dev_find_slot(3, PCI_DEVFN(0x2,1));
                 if (dev) {
                         base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -110,82 +121,77 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
                 }
 	}
   
-	/* ISA Ints:	     Type	Polarity    	    Trigger		   Bus ID   IRQ	 APIC ID    PIN# */
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, 0x2, 0x0);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, 0x2, 0x1);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, 0x2, 0x2);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, 0x2, 0x3);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, 0x2, 0x4);
-  	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x5, 0x2, 0x5);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, 0x2, 0x6);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, 0x2, 0x7);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, 0x2, 0x8);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, 0x2, 0xc);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, 0x2, 0xd);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, 0x2, 0xe);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, 0x2, 0xf);
-
-	/* PCI Ints:	     Type	Polarity    	    Trigger		  Bus ID      PCIDEVNUM|IRQ  APIC ID PIN# */
-	// Integrated SMBus 2.0
-        smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
-	// Integrated AMD AC97 Audio
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
-
-	// Integrated AMD USB
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
-
-	// Onboard Serial ATA        
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11);
-	// Onboard Firewire
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x2, 0x13);
-        
-	// Onboard Broadcom NIC
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x09<<2)|0, 0x3, 0x0);
-
-	// AGP Display Adapter
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1,         0x0, 0x2, 0x10);
-
-	//Slot 5 PCI 32
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x2, 0x10);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x2, 0x11);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x2, 0x12);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x2, 0x13);
-
-	//Slot 3 PCIX 100/66
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|0, 0x3, 0x3);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|1, 0x3, 0x0);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|2, 0x3, 0x1);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|3, 0x3, 0x2);
-
-	//Slot 4 PCIX 100/66        
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|0, 0x3, 0x2);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|1, 0x3, 0x3);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|2, 0x3, 0x0);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|3, 0x3, 0x1);
-
-	//Slot 1 PCI-X 133/100/66
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|0, 0x4, 0x0);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|1, 0x4, 0x1);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|2, 0x4, 0x2);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|3, 0x4, 0x3);
-
-	//Slot 2 PCI-X 133/100/66
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|0, 0x4, 0x1);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|1, 0x4, 0x2);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|2, 0x4, 0x3);
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|3, 0x4, 0x0);
-
-	/*Local Ints:	     Type	Polarity    	    Trigger		  Bus ID   IRQ	APIC ID	     PIN# */
+/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
+*/	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, 0x2, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, 0x2, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, 0x2, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, 0x2, 0x4);
+  	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x5, 0x2, 0x5);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, 0x2, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, 0x2, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, 0x2, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, 0x2, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, 0x2, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, 0x2, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, 0x2, 0xf);
+//??? What
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (4<<2)|3, 0x2, 0x13);
+//Onboard AMD AC97 Audio ???
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (4<<2)|1, 0x2, 0x11);
+// Onboard AMD USB
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13);
+
+//  AGP Display Adapter
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, 0x2, 0x10);
+
+// Onboard Serial ATA        
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11);
+//Onboard Firewire
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x2, 0x13);
+//Onboard Broadcom NIC
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0);
+
+//Slot 5 PCI 32
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x2, 0x10);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x2, 0x11);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x2, 0x12); //
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x2, 0x13); //
+
+//Slot 3 PCIX 100/66
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, 0x3, 0x3);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, 0x3, 0x0);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, 0x3, 0x1);//
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, 0x3, 0x2);//
+
+//Slot 4 PCIX 100/66        
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, 0x3, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, 0x3, 0x3);//
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, 0x3, 0x0);//
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|3, 0x3, 0x1);//
+
+//Slot 1 PCI-X 133/100/66
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x4, 0x0);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, 0x4, 0x1);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x4, 0x2); //
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x4, 0x3); //
+
+//Slot 2 PCI-X 133/100/66
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, 0x4, 0x1);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, 0x4, 0x2);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, 0x4, 0x3);//
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, 0x4, 0x0);//
+
+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_intsrc(mc, mp_NMI, 	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
-
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 	printk_debug("Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
+		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }