Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 41 insertions, 41 deletions

diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb
index f8dc2215d9..7cdc728fbb 100644
--- a/src/mainboard/tyan/s2885/devicetree.cb
+++ b/src/mainboard/tyan/s2885/devicetree.cb
@@ -14,11 +14,11 @@ chip northbridge/amd/amdk8/root_complex
 				end
 			end
 			device pci 18.0 on end # LDT1
-			device pci 18.0 on #  northbridge 
+			device pci 18.0 on #  northbridge
 				#  devices on link 2, link 2 == LDT 2
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
-					device pci 0.0 on 
+					device pci 0.0 on
                                                 device pci 9.0 on end # broadcom 5703
 					end
 					device pci 0.1 on end
@@ -67,7 +67,7 @@ chip northbridge/amd/amdk8/root_complex
 								io 0x60 = 0x220
 								io 0x62 = 0x300
 								irq 0x70 = 9
-							end						
+							end
                 	        			device pnp 2e.8 off end #  GPIO2
                 	        			device pnp 2e.9 off end #  GPIO3
                 	        			device pnp 2e.a off end #  ACPI
@@ -82,36 +82,36 @@ chip northbridge/amd/amdk8/root_complex
 					device pci 1.3 on
                                                 chip drivers/generic/generic #dimm 0-0-0
                                                         device i2c 50 on end
-                                                end              
+                                                end
                                                 chip drivers/generic/generic #dimm 0-0-1
                                                         device i2c 51 on end
-                                                end     
+                                                end
                                                 chip drivers/generic/generic #dimm 0-1-0
                                                         device i2c 52 on end
-                                                end             
+                                                end
                                                 chip drivers/generic/generic #dimm 0-1-1
                                                         device i2c 53 on end
-                                                end              
+                                                end
                                                 chip drivers/generic/generic #dimm 1-0-0
                                                         device i2c 54 on end
-                                                end     
+                                                end
                                                 chip drivers/generic/generic #dimm 1-0-1
                                                         device i2c 55 on end
                                                 end
                                                 chip drivers/generic/generic #dimm 1-1-0
                                                         device i2c 56 on end
-                                                end     
+                                                end
                                                 chip drivers/generic/generic #dimm 1-1-1
                                                         device i2c 57 on end
-                                                end 
+                                                end
 					end # acpi
 					device pci 1.5 on end
 					device pci 1.6 off end
                 	                register "ide0_enable" = "1"
                 	                register "ide1_enable" = "1"
 				end
-			end #  device pci 18.0 
-			
+			end #  device pci 18.0
+
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
@@ -119,9 +119,9 @@ chip northbridge/amd/amdk8/root_complex
 
 	end #pci_domain
 
-#        chip drivers/generic/debug 
+#        chip drivers/generic/debug
 #                device pnp 0.0 off end
-#                device pnp 0.1 off end 
+#                device pnp 0.1 off end
 #                device pnp 0.2 off end
 #                device pnp 0.3 off end
 #		device pnp 0.4 off end
diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c
index de4deb23d3..a511afa395 100644
--- a/src/mainboard/tyan/s2885/get_bus_conf.c
+++ b/src/mainboard/tyan/s2885/get_bus_conf.c
@@ -24,7 +24,7 @@ unsigned apicid_8111 ;
 unsigned apicid_8131_1;
 unsigned apicid_8131_2;
 
-unsigned pci1234x[] = 
+unsigned pci1234x[] =
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
 	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
@@ -36,7 +36,7 @@ unsigned pci1234x[] =
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] = 
+unsigned hcdnx[] =
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
 	0x20202020,
 	0x20202020,
@@ -73,7 +73,7 @@ void get_bus_conf(void)
         }
 
         get_sblk_pci1234();
-	
+
 	sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
 	sbdn3 = sysconf.hcdn[0] & 0xff;
 	sbdn5 = sysconf.hcdn[1] & 0xff;
@@ -135,8 +135,8 @@ void get_bus_conf(void)
 /*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(3);
-#else 
-	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
 	apicid_8111 = apicid_base+0;
 	apicid_8131_1 = apicid_base+1;
diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c
index f9a358e125..b272fda532 100644
--- a/src/mainboard/tyan/s2885/irq_tables.c
+++ b/src/mainboard/tyan/s2885/irq_tables.c
@@ -1,4 +1,4 @@
-/* This file was generated by getpir.c, do not modify! 
+/* This file was generated by getpir.c, do not modify!
    (but if you do, please run checkpir on it to verify)
    Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
 
@@ -12,11 +12,11 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
 		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
 		uint8_t slot, uint8_t rfu)
 {
-        pirq_info->bus = bus; 
+        pirq_info->bus = bus;
         pirq_info->devfn = devfn;
                 pirq_info->irq[0].link = link0;
                 pirq_info->irq[0].bitmap = bitmap0;
@@ -65,22 +65,22 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
-	
+
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version  = PIRQ_VERSION;
-	
+
 	pirq->rtr_bus = bus_8111_0;
 	pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
 
 	pirq->exclusive_irqs = 0;
-	
+
 	pirq->rtr_vendor = 0x1022;
 	pirq->rtr_device = 0x746b;
 
 	pirq->miniport_data = 0;
 
 	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-	
+
 	pirq_info = (void *) ( &pirq->checksum + 1);
 	slot_num = 0;
 //pci bridge
@@ -90,14 +90,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 //        write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 //        pirq_info++; slot_num++;
 //agp bridge
-        write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 
+        write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 
         pirq_info++; slot_num++;
-             
-	pirq->size = 32 + 16 * slot_num; 
+
+	pirq->size = 32 + 16 * slot_num;
 
         for (i = 0; i < pirq->size; i++)
-                sum += v[i];	
+                sum += v[i];
 
 	sum = pirq->checksum - sum;
 
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index d096b07905..87c812fb13 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
 			}
                 }
 	}
-  
+
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
 */	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_8111, 0x1);
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_8111, 0xf);
 //??? What
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13);
-//Onboard AMD AC97 Audio 
+//Onboard AMD AC97 Audio
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11);
 // Onboard AMD USB
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
 //  AGP Display Adapter
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10);
 
-//Onboard Serial ATA        
+//Onboard Serial ATA
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11);
 //Onboard Firewire
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x13);
@@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v)
         }
 
 
-//Slot 4 PCIX 100/66        
+//Slot 4 PCIX 100/66
         for(i=0;i<4;i++) {
                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26
         }
diff --git a/src/mainboard/tyan/s2885/resourcemap.c b/src/mainboard/tyan/s2885/resourcemap.c
index 4a686020c8..af0ccabeb8 100644
--- a/src/mainboard/tyan/s2885/resourcemap.c
+++ b/src/mainboard/tyan/s2885/resourcemap.c
@@ -144,7 +144,7 @@ static void setup_s2885_resource_map(void)
 		 *	   1 = base/limit registers i are read-only
 		 * [ 7: 4] Reserved
 		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
 		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -200,7 +200,7 @@ static void setup_s2885_resource_map(void)
 		 * [ 3: 2] Reserved
 		 * [ 4: 4] VGA Enable
 		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
 		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 		 * [ 5: 5] ISA Enable
 		 *	   0 = ISA matches Disabled
@@ -208,7 +208,7 @@ static void setup_s2885_resource_map(void)
 		 *	       from matching agains this base/limit pair
 		 * [11: 6] Reserved
 		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n 
+		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index 7513c14e1b..f7ea579f6e 100644
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -1,4 +1,4 @@
- 
+
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -71,7 +71,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 
  /* tyan does not want the default */
-#include "resourcemap.c" 
+#include "resourcemap.c"
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
@@ -119,13 +119,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         }
 
 //	post_code(0x32);
-	
+
  	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-	
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);