Tyan update to work with new CPU Config

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

9 files changed, 573 insertions, 338 deletions

diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
index 721badb52a..5064b781f7 100644
--- a/src/mainboard/tyan/s2885/Config.lb
+++ b/src/mainboard/tyan/s2885/Config.lb
@@ -1,268 +1,220 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
 ##
-default HAVE_HARD_RESET=1
-default HARD_RESET_BUS=3
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-###
-### Build code to export a programmable irq routing table
-###
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
 
 ##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
 ##
-default HAVE_MP_TABLE=1
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Build code to export a CMOS option table
+## Compute where this copy of linuxBIOS will start in the boot rom
 ##
-default HAVE_OPTION_TABLE=1
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-#
-###
-### Build code to setup a generic IOAPIC
-###
-default CONFIG_IOAPIC=1
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
 
-###
-### Clean up the motherboard id strings
-###
-default MAINBOARD_PART_NUMBER="S2885"
-default MAINBOARD_VENDOR="Tyan"
+arch i386 end 
 
-###
-### Set all of the defaults for an x86 architecture
-###
-
-arch i386 end
+##
+## Build the objects we have code for in this directory.
+##
 
-###
-### Build the objects we have code for in this directory.
-###
 driver mainboard.o
-#dir /drvers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551
-#driver ti_firewire.o
-#dir /drivers/vga
-
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
 
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+##
+## Romcc output
+##
+makerule ./failover.E
+	depends "$(MAINBOARD)/failover.c" 
+	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+end
 
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
+makerule ./failover.inc
+	depends "./failover.E ./romcc"
+	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
+
+makerule ./auto.E 
+	depends	"$(MAINBOARD)/auto.c option_table.h " 
+	action	"$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+end
+makerule ./auto.inc 
+	depends "./auto.E ./romcc"
+	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
 if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/i386/reset16.inc 
-	ldscript /cpu/i386/reset16.lds 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
 else
-	mainboardinit cpu/i386/reset32.inc 
-	ldscript /cpu/i386/reset32.lds 
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-#### Should this be in the northbridge code?
+### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
+
+##
+## Include an id string (For safe flashing)
+##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup 
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
-  ldscript /arch/i386/lib/failover.lds 
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
+
 ###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to 
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
 ###
-#
 if USE_FALLBACK_IMAGE
-  mainboardinit ./failover.inc
+	ldscript /arch/i386/lib/failover.lds 
+	mainboardinit ./failover.inc
 end
 
-#
-#
 ###
-### Setup the serial port
+### O.k. We aren't just an intermediary anymore!
 ###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-###
-### Romcc output
-###
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c" 
-	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
-end
 
-makerule ./failover.inc
-	depends "./romcc ./failover.E"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
-end
-
-makerule ./auto.E 
-        depends "$(MAINBOARD)/auto.c option_table.h"
-        action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
-end
-
-makerule ./auto.inc 
-	depends "./romcc ./auto.E"
-	action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" 
-end
-
-mainboardinit cpu/k8/enable_mmx_sse.inc
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
 mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
 
-#
-###
-### Include the secondary Configuration files 
-###
+##
+## Include the secondary Configuration files 
+##
 dir /pc80
 config chip.h
-register "fixup_scsi" = "1"
-register "fixup_vga" = "1"
 
-northbridge amd/amdk8 "mc0"
-        pci 0:18.0
-        pci 0:18.0
-        pci 0:18.0
-        pci 0:18.1
-        pci 0:18.2
-        pci 0:18.3
-        southbridge amd/amd8131 "amd8131" link 2
-                pci 0:0.0
-                pci 0:0.1
-                pci 0:1.0
-                pci 0:1.1
+# sample config for tyan/s2885
+chip northbridge/amd/amdk8
+	device pci_domain 0 on
+		device pci 18.0 on # LDT0
+			chip southbridge/amd/amd8151
+				# the on/off keyword is mandatory
+				device pci 0.0 on end
+				device pci 1.0 on end
+			end
+		end
+		device pci 18.0 on end # LDT1
+		device pci 18.0 on #  northbridge 
+			#  devices on link 2, link 2 == LDT 2
+			chip southbridge/amd/amd8131
+				# the on/off keyword is mandatory
+				device pci 0.0 on end
+				device pci 0.1 on end
+				device pci 1.0 on end
+				device pci 1.1 on end
+			end
+			chip southbridge/amd/amd8111
+				# this "device pci 0.0" is the parent the next one
+				# PCI bridge
+				device pci 0.0 on
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 0.2 off end
+					device pci 1.0 off end
+				end
+				device pci 1.0 on
+					chip superio/winbond/w83627hf
+						device pnp 2e.0 on #  Floppy
+                                 			io 0x60 = 0x3f0
+                                			irq 0x70 = 6
+                                			drq 0x74 = 2
+						end
+                        			device pnp 2e.1 off #  Parallel Port
+                                 			io 0x60 = 0x378
+                                			irq 0x70 = 7
+						end
+                        			device pnp 2e.2 on #  Com1
+                                 			io 0x60 = 0x3f8
+                                			irq 0x70 = 4
+						end
+                        			device pnp 2e.3 off #  Com2
+                                 			io 0x60 = 0x2f8
+                                			irq 0x70 = 3
+						end
+                        			device pnp 2e.5 on #  Keyboard
+                                 			io 0x60 = 0x60
+                                 			io 0x62 = 0x64
+                                			irq 0x70 = 1
+							irq 0x72 = 12
+						end
+                        			device pnp 2e.6 off end #  CIR
+                        			device pnp 2e.7 off end #  GAME_MIDI_GIPO1
+                        			device pnp 2e.8 off end #  GPIO2
+                        			device pnp 2e.9 off end #  GPIO3
+                        			device pnp 2e.a off end #  ACPI
+                        			device pnp 2e.b on #  HW Monitor
+ 				 			io 0x60 = 0x290
+                				end
+					end
+				end
+				device pci 1.1 on end
+				device pci 1.2 on end
+				device pci 1.3 on end
+				device pci 1.5 on end
+				device pci 1.6 off end
+			end
+		end #  device pci 18.0 
+		
+		device pci 18.1 on end
+		device pci 18.2 on end
+		device pci 18.3 on end
+
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
+		end
 	end
-	southbridge amd/amd8111 "amd8111" link 2
-       	       	pci 0:0.0
-	       	pci 0:1.0 on
-	        pci 0:1.1 on
-	        pci 0:1.2 on
-	        pci 0:1.3 on
-	        pci 0:1.5 on
-	        pci 0:1.6 off
-                pci 1:0.0 on
-                pci 1:0.1 on
-                pci 1:0.2 off
-                pci 1:1.0 off
-                superio winbond/w83627hf link 1
-                        pnp 2e.0 on #  Floppy
-                                 io 0x60 = 0x3f0
-                                irq 0x70 = 6
-                                drq 0x74 = 2
-                        pnp 2e.1 off #  Parallel Port
-                                 io 0x60 = 0x378
-                                irq 0x70 = 7
-                        pnp 2e.2 on #  Com1
-                                 io 0x60 = 0x3f8
-                                irq 0x70 = 4
-                        pnp 2e.3 off #  Com2
-                                 io 0x60 = 0x2f8
-                                irq 0x70 = 3
-                        pnp 2e.5 on #  Keyboard
-                                 io 0x60 = 0x60
-                                 io 0x62 = 0x64
-                                irq 0x70 = 1
-				irq 0x72 = 12
-                        pnp 2e.6 off #  CIR
-                        pnp 2e.7 off #  GAME_MIDI_GIPO1
-                        pnp 2e.8 off #  GPIO2
-                        pnp 2e.9 off #  GPIO3
-                        pnp 2e.a off #  ACPI
-                        pnp 2e.b on #  HW Monitor
- 				 io 0x60 = 0x290
-                end
-	end
-        southbridge amd/amd8151 "amd8151" link 0
-                pci 0:0.0
-                pci 0:1.0
-        end
-end
-
-northbridge amd/amdk8 "mc1"
-        pci 0:19.0
-        pci 0:19.0
-        pci 0:19.0
-        pci 0:19.1
-        pci 0:19.2
-        pci 0:19.3
-end
-
-cpu k8 "cpu0"
-	register "ldt0" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
-  	register "ldt2" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
-end
-
-cpu k8 "cpu1"
 end
 
diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c
index e4c99d88ef..8a386ab191 100644
--- a/src/mainboard/tyan/s2885/auto.c
+++ b/src/mainboard/tyan/s2885/auto.c
@@ -1,10 +1,12 @@
 #define ASSEMBLY 1
+ 
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -13,49 +15,57 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/cpu_rev.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 static void hard_reset(void)
 {
-	set_bios_reset();
+        set_bios_reset();
 
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
+        /* enable cf9 */
+        pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+        /* reset */
+        outb(0x0e, 0x0cf9);
 }
 
 static void soft_reset(void)
 {
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+        set_bios_reset();
+        pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
+static void soft2_reset(void)
+{  
+        set_bios_reset();
+        pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
 }
 
 static void memreset_setup(void)
 {
-	if (is_cpu_pre_c0()) {
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-	} else {
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-	}
+   if (is_cpu_pre_c0()) {
+        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
+   }
+   else {
+        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
+   }
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-		udelay(90);
-	}
+   if (is_cpu_pre_c0()) {
+        udelay(800);
+        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+        udelay(90);
+   }
 }
 
 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
@@ -82,21 +92,32 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 	 *     [3] Route to Link 2
 	 */
 
-	uint32_t ret = 0x00010101; /* default row entry */
-
-	/* CPU0 LDT1 <-> LDT1 CPU1 */
+	uint32_t ret=0x00010101; /* default row entry */
+/*
+            (L1)       (L1)  (L2)   
+        CPU1-------------CPU0--------8131------8111
+                          |(L0)
+                          |
+                          |
+                          |
+                          |
+                          |
+                        8151 
+*/
+	/* Link1 of CPU0 to Link1 of CPU1 */
 	static const unsigned int rows_2p[2][2] = {
 		{ 0x00050101, 0x00010404 },
 		{ 0x00010404, 0x00050101 }
 	};
 
-	if (maxnodes > 2) {
+	if(maxnodes>2) {
 		print_debug("this mainboard is only designed for 2 cpus\r\n");
-		maxnodes = 2;
+		maxnodes=2;
 	}
 
-	if (!(node >= maxnodes || row >= maxnodes)) {
-		ret = rows_2p[node][row];
+
+	if (!(node>=maxnodes || row>=maxnodes)) {
+		ret=rows_2p[node][row];
 	}
 
 	return ret;
@@ -112,6 +133,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
+#include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
@@ -121,7 +143,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define FIRST_CPU  1
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
 {
 	static const struct mem_controller cpu[] = {
 #if FIRST_CPU
@@ -150,59 +172,97 @@ static void main(void)
 
 #if 1
         static const struct ht_chain ht_c[] = {
-                {
+                { /* Link 2 of CPU0 */
                         .udev = PCI_DEV(0, 0x18, 0),
                         .upos = 0xc0,
-                        .devreg = 0xe0,
+                        .devreg = 0xe0,  /* Preset bus num in resource map */
                 }, 
-                {
+                { /* Link 0 of CPU0 */
                         .udev = PCI_DEV(0, 0x18, 0),
                         .upos = 0x80,
-                        .devreg = 0xe4,
+                        .devreg = 0xe4,  /* Preset bus num in resource map */
                 },
         };
 #endif
 
         int needs_reset;
-        enable_lapic();
-        init_timer();
-
-        if (cpu_init_detected()) {
-                asm volatile ("jmp __cpu_reset");
-        }
-
-        distinguish_cpu_resets();
-        if (!boot_cpu()) {
-                stop_this_cpu();
-        }
-
+	if (bist == 0) {
+		/* Skip this if there was a built in self test failure */
+		amd_early_mtrr_init();
+	        enable_lapic();
+        	init_timer();
+	
+	        if (cpu_init_detected()) {
+#if 0
+        	        asm volatile ("jmp __cpu_reset");
+#else           
+                /* cpu reset also reset the memtroller ????
+                        need soft_reset to reset all except keep HT link freq and width */
+                	distinguish_cpu_resets();
+                	soft2_reset();
+#endif  
+        	}
+        	distinguish_cpu_resets();
+        	if (!boot_cpu()) {
+                	stop_this_cpu();
+        	}
+	}
+	
         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
 
+	/* Halt if there was a built in self test failure */
+//	report_bist_failure(bist);
+	
         setup_s2885_resource_map();
         needs_reset = setup_coherent_ht_domain();
+#if 0
+        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
+#else
         needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
+#endif
         if (needs_reset) {
                 print_info("ht reset -\r\n");
                 soft_reset();
         }
 
-#if 0
-	print_pci_devices();
-#endif
-
 	enable_smbus();
-
 #if 0
 	dump_spd_registers(&cpu[0]);
 #endif
-
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
 #if 0
 	dump_pci_devices();
+#endif
+#if 0
 	dump_pci_device(PCI_DEV(0, 0x18, 1));
 #endif
+	/* Check all of memory */
+#if 0
+	msr_t msr;
+	msr = rdmsr(TOP_MEM2);
+	print_debug("TOP_MEM2: ");
+	print_debug_hex32(msr.hi);
+	print_debug_hex32(msr.lo);
+	print_debug("\r\n");
+	
+	ram_check(0x00000000, msr.lo+(msr.hi<<32));
+
+#endif
+
+#if 0 
+
+//#if TOTAL_CPUS < 2
+	// Check 16MB of memory @ 0
+	ram_check(0x00000000, 0x00100000);
+//#else
+	// Check 16MB of memory @ 2GB 
+//	ram_check(0x80000000, 0x80100000);
+//#endif
+#endif
+
+
 }
diff --git a/src/mainboard/tyan/s2885/chip.h b/src/mainboard/tyan/s2885/chip.h
index 75251c70b6..0be04051da 100644
--- a/src/mainboard/tyan/s2885/chip.h
+++ b/src/mainboard/tyan/s2885/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_control mainboard_tyan_s2885_control;
+extern struct chip_operations mainboard_tyan_s2885_ops;
 
 struct mainboard_tyan_s2885_config {
 	int fixup_scsi;
diff --git a/src/mainboard/tyan/s2885/cmos.layout b/src/mainboard/tyan/s2885/cmos.layout
index 247715e6ac..ea027282c4 100644
--- a/src/mainboard/tyan/s2885/cmos.layout
+++ b/src/mainboard/tyan/s2885/cmos.layout
@@ -41,6 +41,7 @@ entries
 432	     8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
+445          1       e       1        iommu
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
diff --git a/src/mainboard/tyan/s2885/failover.c b/src/mainboard/tyan/s2885/failover.c
index 95d675bc20..2f63cc85b7 100644
--- a/src/mainboard/tyan/s2885/failover.c
+++ b/src/mainboard/tyan/s2885/failover.c
@@ -4,22 +4,15 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
 #include "pc80/mc146818rtc_early.c"
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
 static unsigned long main(unsigned long bist)
 {
-#else
-static void main(void)
-{
-	unsigned long bist = 0;
-#endif
 	/* Make cerain my local apic is useable */
 	enable_lapic();
 
@@ -61,20 +54,18 @@ static void main(void)
 	}
  normal_image:
 	asm volatile ("jmp __normal_image" 
-		      : /* outputs */ 
-		      : "a" (bist) /* inputs */
-		      : /* clobbers */
-		      );
+		: /* outputs */ 
+		: "a" (bist) /* inputs */
+		: /* clobbers */
+		);
  cpu_reset:
+#if 0
 	asm volatile ("jmp __cpu_reset"
-		      : /* outputs */ 
-		      : "a"(bist) /* inputs */
-		      : /* clobbers */
-		      );
+		: /* outputs */ 
+		: "a"(bist) /* inputs */
+		: /* clobbers */
+		);
+#endif
  fallback_image:
-#if HAVE_REGPARM_SUPPORT
 	return bist;
-#else
-	return;
-#endif
 }
diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c
index f29f486896..4c3c4a3a14 100644
--- a/src/mainboard/tyan/s2885/mainboard.c
+++ b/src/mainboard/tyan/s2885/mainboard.c
@@ -6,38 +6,269 @@
 #include "../../../northbridge/amd/amdk8/northbridge.h"
 #include "chip.h"
 
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
+#if 0
+static void fixup_lsi_53c1030(struct device *pdev)
 {
-	0, 1
-};
+//	uint8_t byte;
+	uint16_t word;
 
-static struct device_operations mainboard_operations = {
-        .read_resources   = root_dev_read_resources,
-        .set_resources    = root_dev_set_resources,
-        .enable_resources = enable_childrens_resources,
-        .init             = 0,
-        .scan_bus         = amdk8_scan_root_bus,
-        .enable           = 0,
-};
+	byte = 1;
+        pci_write_config8(pdev, 0xff, byte);
+           // Set the device id 
+//      pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_LSILOGIC_53C1030);
+           // Set the subsytem vendor id 
+//      pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN);  
+        word = 0x10f1;
+	pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
+            // Set the subsytem id 
+	word = 0x2880;
+        pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
+            // Disable writes to the device id 
+	byte = 0;
+        pci_write_config8(pdev, 0xff, byte);
+
+//	lsi_scsi_init(pdev);
+	
+}
+#endif
+
+#if 0
+static void print_pci_regs(struct device *dev)
+{
+      uint8_t byte;
+      int i;
+
+      for(i=0;i<256;i++) {
+	     byte = pci_read_config8(dev, i);
+   
+             if((i%16)==0) printk_debug("\n%02x:",i);
+             printk_debug(" %02x",byte);
+      }
+      printk_debug("\n");
+	
+//        pci_write_config8(dev, 0x4, byte);
 
-static void enumerate(struct chip *chip)
+}
+#endif
+#if 0
+static void print_mem(void)
 {
-        struct chip *child;
+        unsigned int i;
+	unsigned int low_1MB = 0xf4107000;
+	for(i=low_1MB;i<low_1MB+1024;i++) {
+             if((i%16)==0) printk_debug("\n %08x:",i);
+             printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
+             }
+#if 0
+        for(i=low_1MB;i<low_1MB+1024*4;i++) {
+             if((i%16)==0) printk_debug("\n %08x:",i);
+             printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
+             }
+#endif
+ }
+#endif
+#if 0
+static void amd8111_enable_rom(void)
+{
+        uint8_t byte;
+        struct device *dev;
+
+        /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
+        /* Locate the amd8111 */
+        dev = dev_find_device(0x1022, 0x7468, 0);
 
-	if (chip->control && chip->control->name) {
-		printk_debug("Enumerating: %s\n", chip->control->name);
+        /* Set the 4MB enable bit bit */
+        byte = pci_read_config8(dev, 0x43);
+        byte |= 0x80;
+        pci_write_config8(dev, 0x43, byte);
+}
+#endif
+#if 0
+static void onboard_scsi_fixup(void)
+{
+        struct device *dev;
+#if 1
+	unsigned char i,j,k;
+
+	for(i=0;i<=15;i++) {
+		for(j=0;j<=0x1f;j++) {
+			for (k=0;k<=6;k++){
+				dev = dev_find_slot(i, PCI_DEVFN(j, k));
+				if (dev) {
+			                printk_debug("%02x:%02x:%02x",i,j,k);
+					print_pci_regs(dev);
+        			}
+			}
+		}
 	}
+#endif
+
 
-	/* update device operation for dynamic root */
-        dev_root.ops = &mainboard_operations;
-        chip->dev = &dev_root;
-        chip->bus = 0;
-        for (child = chip->children; child; child = child->next) {
-		child->bus = &dev_root.link[0];
+#if 0
+        dev = dev_find_device(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_53C1030,0);
+        if(!dev) {
+                printk_info("LSI_SCSI_FW_FIXUP: No Device Found!");
+                return;
         }
+
+	lsi_scsi_init(dev); 
+#endif
+//	print_mem();
+//	amd8111_enable_rom();
+}
+#endif
+#if 0
+static void vga_fixup(void) {
+        // we do this right here because:
+        // - all the hardware is working, and some VGA bioses seem to need
+        //   that
+        // - we need page 0 below for linuxbios tables.
+#if CONFIG_REALMODE_IDT == 1
+        printk_debug("INSTALL REAL-MODE IDT\n");
+        setup_realmode_idt();
+#endif
+#if CONFIG_VGABIOS == 1
+        printk_debug("DO THE VGA BIOS\n");
+        do_vgabios(0x0600);
+        post_code(0x93);
+#endif
+
 }
 
-struct chip_control mainboard_tyan_s2885_control = {
-        .enumerate = enumerate,
-        .name      = "Tyan s2885 mainboard ",
+#endif
+ 
+#if 0
+static void
+enable(struct chip *chip, enum chip_pass pass)
+{
+
+        struct mainboard_tyan_s2895_config *conf = 
+		(struct mainboard_tyan_s2895_config *)chip->chip_info;
+
+        switch (pass) {
+		default: break;
+//		case CONF_PASS_PRE_CONSOLE:
+//		case CONF_PASS_PRE_PCI:
+//		case CONF_PASS_POST_PCI:		
+                case CONF_PASS_PRE_BOOT:
+//			if (conf->fixup_scsi)
+//        			onboard_scsi_fixup();
+//			if (conf->fixup_vga)
+//				vga_fixup();
+			printk_debug("mainboard fixup pass %d done\r\n",
+					pass);
+			break;
+	}
+
+}
+#endif
+
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG 
+static void debug_init(device_t dev)
+{
+        unsigned bus;
+        unsigned devfn;
+#if 0
+        for(bus = 0; bus < 256; bus++) {
+                for(devfn = 0; devfn < 256; devfn++) {
+                        int i;
+                        dev = dev_find_slot(bus, devfn);
+                        if (!dev) {
+                                continue;
+                        }
+                        if (!dev->enabled) {
+                                continue;
+                        }
+                        printk_info("%02x:%02x.%0x aka %s\n", 
+                                bus, devfn >> 3, devfn & 7, dev_path(dev));
+                        for(i = 0; i < 256; i++) {
+                                if ((i & 0x0f) == 0) {
+                                        printk_info("%02x:", i);
+                                }
+                                printk_info(" %02x", pci_read_config8(dev, i));
+                                if ((i & 0x0f) == 0xf) {
+                                        printk_info("\n");
+                                }
+                        }
+                        printk_info("\n");
+                }
+        }
+#endif
+#if 0
+        msr_t msr;
+        unsigned index;
+        unsigned eax, ebx, ecx, edx;
+        index = 0x80000007;
+        printk_debug("calling cpuid 0x%08x\n", index);
+        asm volatile(
+                "cpuid"
+                : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+                : "a" (index)
+                );
+        printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+                index, eax, ebx, ecx, edx);
+        if (edx & (3 << 1)) {
+                index = 0xC0010042;
+                printk_debug("Reading msr: 0x%08x\n", index);
+                msr = rdmsr(index);
+                printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+                        index, msr.hi, msr.hi);
+        }
+#endif
+}
+
+static void debug_noop(device_t dummy)
+{
+}
+
+static struct device_operations debug_operations = {
+        .read_resources   = debug_noop,
+        .set_resources    = debug_noop,
+        .enable_resources = debug_noop,
+        .init             = debug_init,
+};
+
+static unsigned int scan_root_bus(device_t root, unsigned int max)
+{
+        struct device_path path;
+        device_t debug;
+        max = root_dev_scan_bus(root, max);
+        path.type = DEVICE_PATH_PNP;
+        path.u.pnp.port   = 0;
+        path.u.pnp.device = 0;
+        debug = alloc_dev(&root->link[1], &path);
+        debug->ops = &debug_operations;
+        return max;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{       
+        root_dev_init(dev);
+        
+//        do_verify_cpu_voltages();
+}
+
+static struct device_operations mainboard_operations = {
+	.read_resources   = root_dev_read_resources,
+	.set_resources    = root_dev_set_resources,
+	.enable_resources = root_dev_enable_resources,
+	.init             = mainboard_init,
+#if !DEBUG
+	.scan_bus         = root_dev_scan_bus,
+#else
+	.scan_bus         = scan_root_bus,
+#endif
+	.enable           = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+	dev_root.ops = &mainboard_operations;
+}
+struct chip_operations mainboard_tyan_s2885_ops = {
+	.name      = "Tyan s2885 mainboard ",
+	.enable_dev = enable_dev, 
 };
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index d9477e2966..b5095a6cce 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -4,7 +4,7 @@
 #include <string.h>
 #include <stdint.h>
 
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
         static const char oem[8] = "TYAN    ";
@@ -37,7 +37,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
         mc->mpe_checksum = 0;
         mc->reserved = 0;
 
-        smp_write_processors(mc, processor_map);
+        smp_write_processors(mc);
 
        {
                 device_t dev;
@@ -107,19 +107,21 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 /*I/O APICs:	APIC ID	Version	State		Address*/
 	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
         {
-                struct pci_dev *dev;
-                uint32_t base;
+                device_t dev;
+		struct resource *res;
                 dev = dev_find_slot(3, PCI_DEVFN(0x1,1));
                 if (dev) {
-                        base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-                        base &= PCI_BASE_ADDRESS_MEM_MASK;
-                        smp_write_ioapic(mc, 3, 0x11, base);
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 0x03, 0x11, res->base);
+			}
                 }
                 dev = dev_find_slot(3, PCI_DEVFN(0x2,1));
                 if (dev) {
-                        base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-                        base &= PCI_BASE_ADDRESS_MEM_MASK;
-                        smp_write_ioapic(mc, 4, 0x11, base);
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 0x04, 0x11, res->base);
+			}
                 }
 	}
   
@@ -197,9 +199,9 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	return smp_next_mpe_entry(mc);
 }
 
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
 	v = smp_write_floating_table(addr);
-	return (unsigned long)smp_write_config_table(v, processor_map);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2885/resourcemap.c b/src/mainboard/tyan/s2885/resourcemap.c
index 31cf8e04a5..2c51f1d114 100644
--- a/src/mainboard/tyan/s2885/resourcemap.c
+++ b/src/mainboard/tyan/s2885/resourcemap.c
@@ -252,8 +252,8 @@ static void setup_s2885_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration regin i
 		 */
-		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06010207,
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000007,
+		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link2 of CPU 0
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070003, // AMD 8151 on link0 of CPU 0
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 	};
diff --git a/src/mainboard/tyan/s2885/ti_firewire.c b/src/mainboard/tyan/s2885/ti_firewire.c
index 15f83c0983..12c4c0d0f9 100644
--- a/src/mainboard/tyan/s2885/ti_firewire.c
+++ b/src/mainboard/tyan/s2885/ti_firewire.c
@@ -25,8 +25,6 @@ static void ti_firewire_init(struct device *dev)
         word |= ((1 << 2) |(1<<4)); // Command: 3--> 17
         pci_write_config16(dev, 0x4, word);
 
-	printk_debug("TI_FIREWIRE_FIXUP:  done  \n");
-	
 }
 
 static struct device_operations ti_firewire_ops  = {