diff options
| author | Yinghai Lu <yinghailu@gmail.com> | 2004-10-27 00:37:30 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2004-10-27 00:37:30 +0000 |
| commit | eefdb038981a0fcc93df5c6c934f8138a43873bb (patch) | |
| tree | 0e1d463b681d3ed4294230a707afce19f81f994c /src/mainboard/tyan/s2885/auto.c | |
| parent | fb198640d8ba755b7022800d0077c41dceae1b94 (diff) | |
S2885 winbond Superio all resource set
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2885/auto.c')
| -rw-r--r-- | src/mainboard/tyan/s2885/auto.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c index 577dca8f1c..333aa90c29 100644 --- a/src/mainboard/tyan/s2885/auto.c +++ b/src/mainboard/tyan/s2885/auto.c @@ -50,22 +50,28 @@ static void soft2_reset(void) static void memreset_setup(void) { +#if 0 if (is_cpu_pre_c0()) { outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 } else { +#endif outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 +#if 0 } +#endif outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { +#if 0 if (is_cpu_pre_c0()) { udelay(800); outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } +#endif } static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) @@ -111,7 +117,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) }; if(maxnodes>2) { - print_debug("this mainboard is only designed for 2 cpus\r\n"); +// print_debug("this mainboard is only designed for 2 cpus\r\n"); maxnodes=2; } |