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| author | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-25 22:04:19 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-25 22:04:19 +0000 |
| commit | 3ff7bdaad7afa8f926eb8e1b6151d34cd467dbb0 (patch) | |
| tree | ce1d82069e1cf4e1d5c26def23ef52c1deca15ab /src/mainboard/tyan/s2885/auto.c | |
| parent | 1621e9303cd9fcd6363553a091358bdfb908b8e9 (diff) | |
new from yh lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2885/auto.c')
| -rw-r--r-- | src/mainboard/tyan/s2885/auto.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c index 628f018ce4..30e3c22097 100644 --- a/src/mainboard/tyan/s2885/auto.c +++ b/src/mainboard/tyan/s2885/auto.c @@ -1,4 +1,5 @@ #define ASSEMBLY 1 + #include <stdint.h> #include <device/pci_def.h> #include <cpu/p6/apic.h> @@ -16,20 +17,24 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "debug.c" +#define REV_B_RESET 0 static void memreset_setup(void) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // BY LYH 28->16 0<<0 --> 1<<0 - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); // BY LYH 29->17 +#if REV_B_RESET==1 + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 +#else + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 +#endif + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { - udelay(800); - /* Set memreset_high */ -// outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); // BY LYH 28->17 - udelay(90); + udelay(800); +#if REV_B_RESET==1 + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 +#endif + udelay(90); } static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) @@ -130,10 +135,6 @@ static void stop_this_cpu(void) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) static void main(void) { - /* - * GPIO28 of 8111 will control H0_MEMRESET_L - * GPIO29 of 8111 will control H1_MEMRESET_L - */ static const struct mem_controller cpu[] = { #if FIRST_CPU { @@ -172,8 +173,6 @@ static void main(void) setup_s2885_resource_map(); setup_coherent_ht_domain(); enumerate_ht_chain(0); - //setup_resource_map_x(); - //enumerate_ht_chain(0); distinguish_cpu_resets(0); #if 0 @@ -186,7 +185,7 @@ static void main(void) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 1 +#if 0 dump_pci_devices(); #endif #if 0 |