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| author | Yinghai Lu <yinghailu@gmail.com> | 2004-10-27 00:37:30 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2004-10-27 00:37:30 +0000 |
| commit | eefdb038981a0fcc93df5c6c934f8138a43873bb (patch) | |
| tree | 0e1d463b681d3ed4294230a707afce19f81f994c /src/mainboard/tyan/s2885/Config.lb | |
| parent | fb198640d8ba755b7022800d0077c41dceae1b94 (diff) | |
S2885 winbond Superio all resource set
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2885/Config.lb')
| -rw-r--r-- | src/mainboard/tyan/s2885/Config.lb | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index 5064b781f7..2bdabea244 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -177,13 +177,20 @@ chip northbridge/amd/amdk8 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x201 + io 0x62 = 0x330 + irq 0x70 = 9 + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 + irq 0x70 = 5 end end end @@ -192,6 +199,8 @@ chip northbridge/amd/amdk8 device pci 1.3 on end device pci 1.5 on end device pci 1.6 off end +# register "ide0_enable" = "1" +# register "ide1_enable" = "1" end end # device pci 18.0 |