Tyan update to work with new CPU Config

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 485 insertions, 288 deletions

diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb
index 0363838328..be79fcebc8 100644
--- a/src/mainboard/tyan/s2882/Config.lb
+++ b/src/mainboard/tyan/s2882/Config.lb
@@ -1,225 +1,215 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-config chip.h
-register "fixup_scsi" = "1" 
-register "fixup_vga" = "1"
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end 
+
+##
+## Build the objects we have code for in this directory.
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
 
 driver mainboard.o
-#dir /drvers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551_ipmi
-dir /drivers/ati/ragexl
-#object reset.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-#
-arch i386 end
-#cpu k8 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/i386/reset16.inc 
-	ldscript /cpu/i386/reset16.lds 
-else
-	mainboardinit cpu/i386/reset32.inc 
-	ldscript /cpu/i386/reset32.lds 
-end
-#
-#### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup 
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
-  ldscript /arch/i386/lib/failover.lds 
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to 
-###
-#
-if USE_FALLBACK_IMAGE
-  mainboardinit ./failover.inc
-end
-
-#
-#
-###
-### Setup the serial port
-###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-#
-###
-### When debugging disable the watchdog timer
-###
-##option MAXIMUM_CONSOLE_LOGLEVEL=7
-#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#
-#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
-#
-###
-### Romcc output
-###
+#object reset.o
 
+##
+## Romcc output
+##
 makerule ./failover.E
 	depends "$(MAINBOARD)/failover.c" 
 	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 end
 
 makerule ./failover.inc
-	depends "./romcc ./failover.E"
-	action "./romcc -O2 -o failover.inc --label-prefix=failover ./failover.E"
+	depends "./failover.E ./romcc"
+	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
 end
 
 makerule ./auto.E 
-        depends "$(MAINBOARD)/auto.c option_table.h"
-        action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+	depends	"$(MAINBOARD)/auto.c option_table.h " 
+	action	"$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 end
 makerule ./auto.inc 
-	depends "./romcc ./auto.E"
-	action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" 
+	depends "./auto.E ./romcc"
+	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
 end
-mainboardinit cpu/k8/enable_mmx_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
-#
-###
-### Include the secondary Configuration files 
-###
 
-northbridge amd/amdk8 "mc0"
-        pci 0:18.0
-        pci 0:18.0
-        pci 0:18.0
-        pci 0:18.1
-        pci 0:18.2
-        pci 0:18.3
-        southbridge amd/amd8131 "amd8131" link 0
-                pci 0:0.0
-                pci 0:0.1
-                pci 0:1.0
-                pci 0:1.1
-        end
-        southbridge amd/amd8111 "amd8111" link 0
-                pci 0:0.0
-                pci 0:1.0 on
-                pci 0:1.1 on
-                pci 0:1.2 on
-                pci 0:1.3 on
-                pci 0:1.5 off
-                pci 0:1.6 off
-                pci 1:0.0 on
-                pci 1:0.1 on
-                pci 1:0.2 off
-                pci 1:1.0 off
-                superio winbond/w83627hf link 1
-                        pnp 2e.0 on #  Floppy
-                                 io 0x60 = 0x3f0
-                                irq 0x70 = 6
-                                drq 0x74 = 2
-                        pnp 2e.1 off #  Parallel Port
-                                 io 0x60 = 0x378
-                                irq 0x70 = 7
-                        pnp 2e.2 on #  Com1
-                                 io 0x60 = 0x3f8
-                                irq 0x70 = 4
-                        pnp 2e.3 off #  Com2
-                                 io 0x60 = 0x2f8
-                                irq 0x70 = 3
-                        pnp 2e.5 on #  Keyboard
-                                 io 0x60 = 0x60
-                                 io 0x62 = 0x64
-                                irq 0x70 = 1
-				irq 0x72 = 12
-                        pnp 2e.6 off #  CIR
-                        pnp 2e.7 off #  GAME_MIDI_GIPO1
-                        pnp 2e.8 off #  GPIO2
-                        pnp 2e.9 off #  GPIO3
-                        pnp 2e.a off #  ACPI
-                        pnp 2e.b on  #  HW Monitor
-				 io 0x60 = 0x290
-                end
-        end
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-northbridge amd/amdk8 "mc1"
-        pci 0:19.0
-        pci 0:19.0
-        pci 0:19.0
-        pci 0:19.1
-        pci 0:19.2
-        pci 0:19.3
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds 
+	mainboardinit ./failover.inc
 end
- 
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files 
+##
 dir /pc80
-#dir /bioscall
-cpu k8 "cpu0"
-  register "ldt0" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
-end
+config chip.h
 
-cpu k8 "cpu1"
+# sample config for tyan/s2882
+chip northbridge/amd/amdk8
+	device pci_domain 0 on
+		device pci 18.0 on #  northbridge 
+			#  devices on link 0, link 0 == LDT 0
+			chip southbridge/amd/amd8131
+				# the on/off keyword is mandatory
+				device pci 0.0 on end
+				device pci 0.1 on end
+				device pci 1.0 on end
+				device pci 1.1 on end
+			end
+			chip southbridge/amd/amd8111
+				# this "device pci 0.0" is the parent the next one
+				# PCI bridge
+				device pci 0.0 on
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 0.2 off end
+					device pci 1.0 off end
+				end
+				device pci 1.0 on
+					chip superio/winbond/w83627hf
+						device pnp 2e.0 on #  Floppy
+                                 			io 0x60 = 0x3f0
+                                			irq 0x70 = 6
+                                			drq 0x74 = 2
+						end
+                        			device pnp 2e.1 off #  Parallel Port
+                                 			io 0x60 = 0x378
+                                			irq 0x70 = 7
+						end
+                        			device pnp 2e.2 on #  Com1
+                                 			io 0x60 = 0x3f8
+                                			irq 0x70 = 4
+						end
+                        			device pnp 2e.3 off #  Com2
+                                 			io 0x60 = 0x2f8
+                                			irq 0x70 = 3
+						end
+                        			device pnp 2e.5 on #  Keyboard
+                                 			io 0x60 = 0x60
+                                 			io 0x62 = 0x64
+                                			irq 0x70 = 1
+							irq 0x72 = 12
+						end
+                        			device pnp 2e.6 off end #  CIR
+                        			device pnp 2e.7 off end #  GAME_MIDI_GIPO1
+                        			device pnp 2e.8 off end #  GPIO2
+                        			device pnp 2e.9 off end #  GPIO3
+                        			device pnp 2e.a off end #  ACPI
+                        			device pnp 2e.b on #  HW Monitor
+ 				 			io 0x60 = 0x290
+                				end
+					end
+				end
+				device pci 1.1 on end
+				device pci 1.2 on end
+				device pci 1.3 on end
+				device pci 1.5 off end
+				device pci 1.6 off end
+			end
+		end #  device pci 18.0 
+	
+                device pci 18.0 on end
+                device pci 18.0 on end
+	
+		device pci 18.1 on end
+		device pci 18.2 on end
+		device pci 18.3 on end
+
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
+		end
+	end
 end
+
diff --git a/src/mainboard/tyan/s2882/auto.c b/src/mainboard/tyan/s2882/auto.c
index bd4a9aa4c5..e2c118ec98 100644
--- a/src/mainboard/tyan/s2882/auto.c
+++ b/src/mainboard/tyan/s2882/auto.c
@@ -1,10 +1,12 @@
 #define ASSEMBLY 1
+
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -13,13 +15,15 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c" 
+#include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c" 
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -38,6 +42,13 @@ static void soft_reset(void)
         set_bios_reset();
         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
 }
+
+static void soft2_reset(void)
+{       
+        set_bios_reset();
+        pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
+}
+ 
  
 #define REV_B_RESET 0
 static void memreset_setup(void)
@@ -86,17 +97,17 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 	 */
 
 	uint32_t ret=0x00010101; /* default row entry */
-
+	/* Link1 of CPU0 to Link1 of CPU1 */
 	static const unsigned int rows_2p[2][2] = {
 		{ 0x00050101, 0x00010404 },
 		{ 0x00010404, 0x00050101 }
 	};
-
+#if 0
 	if(maxnodes>2) {
-		print_debug("this mainboard is only designed for 2 cpus\r\n");
+		printo_debug("this mainboard is only designed for 2 cpus\r\n");
 		maxnodes=2;
 	}
-
+#endif
 
 	if (!(node>=maxnodes || row>=maxnodes)) {
 		ret=rows_2p[node][row];
@@ -115,14 +126,17 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
+
 #define FIRST_CPU  1
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
 {
 	/*
 	 * GPIO28 of 8111 will control H0_MEMRESET_L
@@ -154,18 +168,36 @@ static void main(void)
 	};
         
 	int needs_reset;
-        enable_lapic();
-        init_timer();
-        if (cpu_init_detected()) {
-                asm("jmp __cpu_reset");
-        }
-        distinguish_cpu_resets();
-        if (!boot_cpu()) {
-                stop_this_cpu();
+
+        if (bist == 0) {
+                /* Skip this if there was a built in self test failure */
+                amd_early_mtrr_init();
+                enable_lapic();
+                init_timer();
+
+                if (cpu_init_detected()) {
+#if 0
+                        asm volatile ("jmp __cpu_reset");
+#else 
+                /* cpu reset also reset the memtroller ????
+                        need soft_reset to reset all except keep HT link freq and width */
+                        distinguish_cpu_resets();
+                        soft2_reset();
+#endif
+                }
+                distinguish_cpu_resets();
+                if (!boot_cpu()) {
+                        stop_this_cpu();
+                }
         }
+
         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
+
+        /* Halt if there was a built in self test failure */
+//      report_bist_failure(bist);
+
         setup_default_resource_map();
         needs_reset = setup_coherent_ht_domain();
         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
diff --git a/src/mainboard/tyan/s2882/chip.h b/src/mainboard/tyan/s2882/chip.h
index a23805d043..308683f992 100644
--- a/src/mainboard/tyan/s2882/chip.h
+++ b/src/mainboard/tyan/s2882/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_control mainboard_tyan_s2882_control;
+extern struct chip_operations mainboard_tyan_s2882_ops;
 
 struct mainboard_tyan_s2882_config {
 	int fixup_scsi;
diff --git a/src/mainboard/tyan/s2882/cmos.layout b/src/mainboard/tyan/s2882/cmos.layout
index 247715e6ac..ea027282c4 100644
--- a/src/mainboard/tyan/s2882/cmos.layout
+++ b/src/mainboard/tyan/s2882/cmos.layout
@@ -41,6 +41,7 @@ entries
 432	     8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
+445          1       e       1        iommu
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
diff --git a/src/mainboard/tyan/s2882/failover.c b/src/mainboard/tyan/s2882/failover.c
index b22abfea06..2f63cc85b7 100644
--- a/src/mainboard/tyan/s2882/failover.c
+++ b/src/mainboard/tyan/s2882/failover.c
@@ -4,22 +4,15 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
 #include "pc80/mc146818rtc_early.c"
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
 static unsigned long main(unsigned long bist)
 {
-#else
-static void main(void)
-{
-	unsigned long bist = 0;
-#endif
 	/* Make cerain my local apic is useable */
 	enable_lapic();
 
@@ -60,21 +53,19 @@ static void main(void)
 		goto fallback_image;
 	}
  normal_image:
-	asm("jmp __normal_image" 
+	asm volatile ("jmp __normal_image" 
 		: /* outputs */ 
 		: "a" (bist) /* inputs */
 		: /* clobbers */
 		);
  cpu_reset:
-	asm("jmp __cpu_reset"
+#if 0
+	asm volatile ("jmp __cpu_reset"
 		: /* outputs */ 
 		: "a"(bist) /* inputs */
 		: /* clobbers */
 		);
+#endif
  fallback_image:
-#if HAVE_REGPARM_SUPPORT
 	return bist;
-#else
-	return;
-#endif
 }
diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c
index 27b7fc5bb4..059f7210a9 100644
--- a/src/mainboard/tyan/s2882/irq_tables.c
+++ b/src/mainboard/tyan/s2882/irq_tables.c
@@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = {
 	0x746b,         /* Device */
 	0,         /* Crap (miniport) */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x8d,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	0xff,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
 		{1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
 		{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
diff --git a/src/mainboard/tyan/s2882/mainboard.c b/src/mainboard/tyan/s2882/mainboard.c
index 914d302422..6a9c4bc8bd 100644
--- a/src/mainboard/tyan/s2882/mainboard.c
+++ b/src/mainboard/tyan/s2882/mainboard.c
@@ -5,12 +5,7 @@
 #include <device/pci_ops.h>
 #include "../../../northbridge/amd/amdk8/northbridge.h"
 #include "chip.h"
-//#include <part/mainboard.h>
-//#include "lsi_scsi.c"
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
-{
-	0,1
-};
+
 #if 0
 static void fixup_lsi_53c1030(struct device *pdev)
 {
@@ -36,7 +31,7 @@ static void fixup_lsi_53c1030(struct device *pdev)
 	
 }
 #endif
-//extern static void lsi_scsi_init(struct device *dev);
+
 #if 0
 static void print_pci_regs(struct device *dev)
 {
@@ -46,7 +41,7 @@ static void print_pci_regs(struct device *dev)
       for(i=0;i<256;i++) {
 	     byte = pci_read_config8(dev, i);
    
-             if((i%16)==0) printk_info("\n%02x:",i);
+             if((i%16)==0) printk_debug("\n%02x:",i);
              printk_debug(" %02x",byte);
       }
       printk_debug("\n");
@@ -58,17 +53,18 @@ static void print_pci_regs(struct device *dev)
 #if 0
 static void print_mem(void)
 {
-        int i;
-	int low_1MB = 0;
-	for(i=low_1MB;i<low_1MB+1024*4;i++) {
+        unsigned int i;
+	unsigned int low_1MB = 0xf4107000;
+	for(i=low_1MB;i<low_1MB+1024;i++) {
              if((i%16)==0) printk_debug("\n %08x:",i);
              printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
              }
-
+#if 0
         for(i=low_1MB;i<low_1MB+1024*4;i++) {
              if((i%16)==0) printk_debug("\n %08x:",i);
              printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
              }
+#endif
  }
 #endif
 #if 0
@@ -87,12 +83,14 @@ static void amd8111_enable_rom(void)
         pci_write_config8(dev, 0x43, byte);
 }
 #endif
+#if 0
 static void onboard_scsi_fixup(void)
 {
-       struct device *dev;
+        struct device *dev;
+#if 1
 	unsigned char i,j,k;
-#if 0 
-	for(i=0;i<=5;i++) {
+
+	for(i=0;i<=15;i++) {
 		for(j=0;j<=0x1f;j++) {
 			for (k=0;k<=6;k++){
 				dev = dev_find_slot(i, PCI_DEVFN(j, k));
@@ -118,7 +116,8 @@ static void onboard_scsi_fixup(void)
 //	print_mem();
 //	amd8111_enable_rom();
 }
-/*
+#endif
+#if 0
 static void vga_fixup(void) {
         // we do this right here because:
         // - all the hardware is working, and some VGA bioses seem to need
@@ -130,63 +129,146 @@ static void vga_fixup(void) {
 #endif
 #if CONFIG_VGABIOS == 1
         printk_debug("DO THE VGA BIOS\n");
-        do_vgabios();
+        do_vgabios(0x0600);
         post_code(0x93);
 #endif
 
 }
- */
 
+#endif
+ 
+#if 0
 static void
 enable(struct chip *chip, enum chip_pass pass)
 {
 
-        struct mainboard_tyan_s2882_config *conf = 
-		(struct mainboard_tyan_s2882_config *)chip->chip_info;
+        struct mainboard_tyan_s2895_config *conf = 
+		(struct mainboard_tyan_s2895_config *)chip->chip_info;
 
         switch (pass) {
 		default: break;
 //		case CONF_PASS_PRE_CONSOLE:
 //		case CONF_PASS_PRE_PCI:
-		case CONF_PASS_POST_PCI:		
+//		case CONF_PASS_POST_PCI:		
                 case CONF_PASS_PRE_BOOT:
 //			if (conf->fixup_scsi)
 //        			onboard_scsi_fixup();
 //			if (conf->fixup_vga)
 //				vga_fixup();
-//			printk_debug("mainboard fixup pass %d done\r\n",pass);
+			printk_debug("mainboard fixup pass %d done\r\n",
+					pass);
 			break;
 	}
 
 }
-void final_mainboard_fixup(void)
+#endif
+
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG 
+static void debug_init(device_t dev)
 {
+        unsigned bus;
+        unsigned devfn;
 #if 0
-        enable_ide_devices();
+        for(bus = 0; bus < 256; bus++) {
+                for(devfn = 0; devfn < 256; devfn++) {
+                        int i;
+                        dev = dev_find_slot(bus, devfn);
+                        if (!dev) {
+                                continue;
+                        }
+                        if (!dev->enabled) {
+                                continue;
+                        }
+                        printk_info("%02x:%02x.%0x aka %s\n", 
+                                bus, devfn >> 3, devfn & 7, dev_path(dev));
+                        for(i = 0; i < 256; i++) {
+                                if ((i & 0x0f) == 0) {
+                                        printk_info("%02x:", i);
+                                }
+                                printk_info(" %02x", pci_read_config8(dev, i));
+                                if ((i & 0x0f) == 0xf) {
+                                        printk_info("\n");
+                                }
+                        }
+                        printk_info("\n");
+                }
+        }
+#endif
+#if 0
+        msr_t msr;
+        unsigned index;
+        unsigned eax, ebx, ecx, edx;
+        index = 0x80000007;
+        printk_debug("calling cpuid 0x%08x\n", index);
+        asm volatile(
+                "cpuid"
+                : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+                : "a" (index)
+                );
+        printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+                index, eax, ebx, ecx, edx);
+        if (edx & (3 << 1)) {
+                index = 0xC0010042;
+                printk_debug("Reading msr: 0x%08x\n", index);
+                msr = rdmsr(index);
+                printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+                        index, msr.hi, msr.hi);
+        }
 #endif
 }
-static struct device_operations mainboard_operations = {
-        .read_resources   = root_dev_read_resources,
-        .set_resources    = root_dev_set_resources,
-        .enable_resources = enable_childrens_resources,
-        .init             = 0,
-        .scan_bus         = amdk8_scan_root_bus,
-        .enable           = 0,
+
+static void debug_noop(device_t dummy)
+{
+}
+
+static struct device_operations debug_operations = {
+        .read_resources   = debug_noop,
+        .set_resources    = debug_noop,
+        .enable_resources = debug_noop,
+        .init             = debug_init,
 };
 
-static void enumerate(struct chip *chip)
+static unsigned int scan_root_bus(device_t root, unsigned int max)
 {
-        struct chip *child;
-        dev_root.ops = &mainboard_operations;
-        chip->dev = &dev_root;
-        chip->bus = 0;
-        for(child = chip->children; child; child = child->next) {
-                child->bus = &dev_root.link[0];
-        }
+        struct device_path path;
+        device_t debug;
+        max = root_dev_scan_bus(root, max);
+        path.type = DEVICE_PATH_PNP;
+        path.u.pnp.port   = 0;
+        path.u.pnp.device = 0;
+        debug = alloc_dev(&root->link[1], &path);
+        debug->ops = &debug_operations;
+        return max;
 }
-struct chip_control mainboard_tyan_s2882_control = {
-        .enable = enable,
-        .enumerate = enumerate,
-        .name      = "Tyan s2882 mainboard ",
+#endif
+
+static void mainboard_init(device_t dev)
+{       
+        root_dev_init(dev);
+        
+//        do_verify_cpu_voltages();
+}
+
+static struct device_operations mainboard_operations = {
+	.read_resources   = root_dev_read_resources,
+	.set_resources    = root_dev_set_resources,
+	.enable_resources = root_dev_enable_resources,
+	.init             = mainboard_init,
+#if !DEBUG
+	.scan_bus         = root_dev_scan_bus,
+#else
+	.scan_bus         = scan_root_bus,
+#endif
+	.enable           = 0,
 };
 
+static void enable_dev(struct device *dev)
+{
+	dev_root.ops = &mainboard_operations;
+}
+struct chip_operations mainboard_tyan_s2882_ops = {
+	.name      = "Tyan s2882 mainboard ",
+	.enable_dev = enable_dev, 
+};
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 30b61d1642..4bf298923d 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -1,10 +1,13 @@
 #include <console/console.h>
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
+#include <device/pci_ids.h>
 #include <string.h>
 #include <stdint.h>
 
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+#define ASSIGN_IRQ 0
+
+void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
         static const char oem[8] = "TYAN    ";
@@ -34,7 +37,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
         mc->mpe_checksum = 0;
         mc->reserved = 0;
 
-        smp_write_processors(mc, processor_map);
+        smp_write_processors(mc);
         {
                 device_t dev;
 
@@ -85,20 +88,23 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 /*I/O APICs:	APIC ID	Version	State		Address*/
 	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
         {
-                struct pci_dev *dev;
-                uint32_t base;
+                device_t dev;
+                struct resource *res;
                 dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
                 if (dev) {
-                        base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-                        base &= PCI_BASE_ADDRESS_MEM_MASK;
-                        smp_write_ioapic(mc, 3, 0x11, base);
+                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                        if (res) {
+                                smp_write_ioapic(mc, 0x03, 0x11, res->base);
+                        }
                 }
                 dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
                 if (dev) {
-                        base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-                        base &= PCI_BASE_ADDRESS_MEM_MASK;
-                        smp_write_ioapic(mc, 4, 0x11, base);
+                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                        if (res) {
+                                smp_write_ioapic(mc, 0x04, 0x11, res->base);
+                        }
                 }
+
 	}
   
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
@@ -115,27 +121,82 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
 
-
+#if ASSIGN_IRQ 
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (4<<2)|3, 0x2, 0x13);
+
+	{
+		device_t dev;
+        	dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x746b, 0);
+        	if (dev) {
+                	/* initialize PCI interupts - these assignments depend
+                   	on the PCB routing of PINTA-D 
+
+                   	PINTA = IRQ5
+                   	PINTB = IRQ9
+                   	PINTC = IRQ11
+                   	PINTD = IRQ10
+                	*/
+                	pci_write_config16(dev, 0x56, 0xab95);
+		}
+        }
+#endif
+
+#if ASSIGN_IRQ
+        printk_info("setting Onboard AMD Southbridge \n");
+        static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 };
+        pci_assign_irqs(1, 4, slotIrqs_1_4);
+#endif
 	
 //On Board AMD USB
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13);
 
+#if ASSIGN_IRQ
+        printk_info("setting Onboard AMD USB \n");
+        static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 };
+        pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0);
+#endif
+
 //On Board ATI Display Adapter
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, 0x2, 0x12);
 
+#if ASSIGN_IRQ
+        printk_info("setting Onboard ATI Display Adapter\n");
+        static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 };
+        pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6);
+#endif
+
 #if 1
 //Slot 5 PCI 32
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, 0x2, 0x10);
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, 0x2, 0x11);
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, 0x2, 0x12); //
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, 0x2, 0x13); //
+
+#if ASSIGN_IRQ
+        printk_info("setting Slot 5 \n");
+        static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 };
+        pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4);
+#endif
+
 #endif
 //Onboard SI Serial ATA
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, 0x2, 0x13);
+
+#if ASSIGN_IRQ
+        printk_info("setting Onboard SI Serail ATA\n");
+        static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 };
+        pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5);
+#endif
+
 //Onboard Intel 82551 10/100M NIC
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, 0x2, 0x12);
 
+#if ASSIGN_IRQ
+        printk_info("setting Onboard Intel NIC\n");
+        static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 };
+        pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8);
+#endif
+
 #if 1
 //Slot 3 PCIX 100/66
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, 0x3, 0x3);
@@ -143,18 +204,46 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, 0x3, 0x1);//
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, 0x3, 0x2);//
 
+#if ASSIGN_IRQ
+        printk_info("setting Slot 3\n");
+        static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 };
+        pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3);
+#endif
+
 //Slot 4 PCIX 100/66        
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, 0x3, 0x2);
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, 0x3, 0x3);//
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, 0x3, 0x0);//
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, 0x3, 0x1);//
+
+#if ASSIGN_IRQ
+        printk_info("setting Slot 4\n");
+        static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 };
+        pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2);
+#endif
+
 #endif
 //Onboard adaptec scsi
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, 0x3, 0x0);
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, 0x3, 0x1);
+
+#if ASSIGN_IRQ
+        printk_info("setting Onboard Adaptec  SCSI\n");
+        static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 };
+        pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6);
+#endif
+
 //On Board NIC
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0);
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, 0x3, 0x1);
+
+
+#if ASSIGN_IRQ
+        printk_info("setting Onboard Broadcom NIC\n");
+	static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 };	
+        pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9);
+#endif
+
 #if 1
 //Slot 1 PCI-X 133/100/66
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x4, 0x0);
@@ -162,12 +251,24 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x4, 0x2); //
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x4, 0x3); //
 
+#if ASSIGN_IRQ
+        printk_info("setting Slot 1\n");
+        static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 };
+        pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3);
+#endif
+
 //Slot 2 PCI-X 133/100/66
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, 0x4, 0x1);
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, 0x4, 0x2);
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, 0x4, 0x3);//
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, 0x4, 0x0);//
 
+#if ASSIGN_IRQ
+        printk_info("setting Slot 2\n");
+        static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 };
+        pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1);
+#endif
+
 #endif
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
@@ -182,9 +283,9 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	return smp_next_mpe_entry(mc);
 }
 
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
 	v = smp_write_floating_table(addr);
-	return (unsigned long)smp_write_config_table(v, processor_map);
+	return (unsigned long)smp_write_config_table(v);
 }