diff options
author | Stefan Reinauer <stepan@openbios.org> | 2005-12-02 23:16:01 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2005-12-02 23:16:01 +0000 |
commit | 373511b2f96807d7a7a6b0b34ad3e7519c311aee (patch) | |
tree | 0f56ce6eaf3d93c68c44de1dab5d1c01c2fa276d /src/mainboard/tyan/s2850 | |
parent | 563fc1686075d370cf4f49f85e21c546c52d2a05 (diff) |
issue 41 - fix up motherboard compilation. There's always hope.
1201_ht_bus0_dev0_fidvid_mb.diff part 1
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2850')
-rw-r--r-- | src/mainboard/tyan/s2850/Options.lb | 8 | ||||
-rw-r--r-- | src/mainboard/tyan/s2850/auto.c | 2 | ||||
-rw-r--r-- | src/mainboard/tyan/s2850/cache_as_ram_auto.c | 23 |
3 files changed, 23 insertions, 10 deletions
diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb index 646293e20e..d6db7c1c74 100644 --- a/src/mainboard/tyan/s2850/Options.lb +++ b/src/mainboard/tyan/s2850/Options.lb @@ -52,7 +52,7 @@ uses OBJCOPY uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_E0_MEM_HOLE_SIZEK +uses K8_HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -71,7 +71,9 @@ default ROM_SIZE=524288 ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=131072 +#default FALLBACK_SIZE=131072 +#256K +default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot @@ -120,7 +122,7 @@ default CONFIG_LOGICAL_CPUS=1 default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_E0_MEM_HOLE_SIZEK=0x100000 +default K8_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 diff --git a/src/mainboard/tyan/s2850/auto.c b/src/mainboard/tyan/s2850/auto.c index 0b9012aca8..e0d85dbd56 100644 --- a/src/mainboard/tyan/s2850/auto.c +++ b/src/mainboard/tyan/s2850/auto.c @@ -19,7 +19,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "northbridge/amd/amdk8/cpu_rev.c" +#include <cpu/amd/model_fxx_rev.h> #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/tyan/s2850/cache_as_ram_auto.c b/src/mainboard/tyan/s2850/cache_as_ram_auto.c index b7a39047f2..38aba17835 100644 --- a/src/mainboard/tyan/s2850/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2850/cache_as_ram_auto.c @@ -13,7 +13,18 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/cpu_rev.c" +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + +#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -134,9 +145,11 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); + /* Setup the ck804 */ amd8111_enable_rom(); /* Is this a deliberate reset by the bios */ +// post_code(0x22); if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } @@ -148,12 +161,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) goto fallback_image; } normal_image: +// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ ); fallback_image: +// post_code(0x25); ; } #endif @@ -191,6 +206,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } +// post_code(0x32); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); @@ -200,10 +216,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) report_bist_failure(bist); setup_default_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); @@ -211,7 +223,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // It is said that we should start core1 after all core0 launched start_other_cores(); #endif - // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); if (needs_reset) { |