Major merge of YhLu's code from 2004/04/20: add s2875, various other updates,

cleanups. Drop "driver" code from mainboard directories and use them from the
driver directory instead


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 49 insertions, 25 deletions

diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb
index ad189c9202..4b1375f4c4 100644
--- a/src/mainboard/tyan/s2850/Config.lb
+++ b/src/mainboard/tyan/s2850/Config.lb
@@ -1,6 +1,9 @@
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
 uses MAINBOARD
 uses ARCH
 uses HARD_RESET_BUS
@@ -22,13 +25,19 @@ register "fixup_scsi" = "1"
 register "fixup_vga" = "1"
 
 
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
 driver mainboard.o
-driver adaptec_scsi.o
-driver promise_sata.o
-driver intel_nic.o
-driver broadcom_nic.o
+#driver adaptec_scsi.o
+#driver si_sata.o
+#driver intel_nic_ipmi.o
+#driver broadcom_nic_ipmi.o
 #object reset.o
-#object static_devices.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #
@@ -44,6 +53,7 @@ arch i386 end
 ###
 mainboardinit cpu/i386/entry16.inc
 mainboardinit cpu/i386/entry32.inc
+mainboardinit cpu/i386/bist32.inc
 ldscript /cpu/i386/entry16.lds
 ldscript /cpu/i386/entry32.lds
 #
@@ -95,9 +105,9 @@ end
 ###
 ### Setup the serial port
 ###
-#mainboardinit superiowinbond/w83627hf/setup_serial.inc
 mainboardinit pc80/serial.inc
 mainboardinit arch/i386/lib/console.inc
+mainboardinit cpu/i386/bist32_fail.inc
 #
 ####
 #### O.k. We aren't just an intermediary anymore!
@@ -114,9 +124,6 @@ mainboardinit arch/i386/lib/console.inc
 ###
 ### Romcc output
 ###
-#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
-#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
-#mainboardinit .failover.inc
 
 makerule ./failover.E
 	depends "$(MAINBOARD)/failover.c" 
@@ -125,16 +132,16 @@ end
 
 makerule ./failover.inc
 	depends "./romcc ./failover.E"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
+	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c" 
-	action	"$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+        depends "$(MAINBOARD)/auto.c option_table.h"
+        action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 end
 makerule ./auto.inc 
 	depends "./romcc ./auto.E"
-	action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" 
-#	action	"./romcc -mcpu=k8  -O ./auto.E > auto.inc"
+	action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" 
 end
 mainboardinit cpu/k8/enable_mmx_sse.inc
 mainboardinit ./auto.inc
@@ -143,6 +150,7 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
 ###
 ### Include the secondary Configuration files 
 ###
+
 northbridge amd/amdk8 "mc0"
         pci 0:18.0
         pci 0:18.0
@@ -162,22 +170,38 @@ northbridge amd/amdk8 "mc0"
                 pci 1:0.1 on
                 pci 1:0.2 on
                 pci 1:1.0 off
+                superio winbond/w83627hf link 1
+                        pnp 2e.0 on #  Floppy
+                                 io 0x60 = 0x3f0
+                                irq 0x70 = 6
+                                drq 0x74 = 2
+                        pnp 2e.1 off #  Parallel Port
+                                 io 0x60 = 0x378
+                                irq 0x70 = 7
+                        pnp 2e.2 on #  Com1
+                                 io 0x60 = 0x3f8
+                                irq 0x70 = 4
+                        pnp 2e.3 off #  Com2
+                                 io 0x60 = 0x2f8
+                                irq 0x70 = 3
+                        pnp 2e.5 on #  Keyboard
+                                 io 0x60 = 0x60
+                                 io 0x62 = 0x64
+                                irq 0x70 = 1
+				irq 0x72 = 12
+                        pnp 2e.6 off #  CIR
+                        pnp 2e.7 off #  GAME_MIDI_GIPO1
+                        pnp 2e.8 off #  GPIO2
+                        pnp 2e.9 off #  GPIO3
+                        pnp 2e.a off #  ACPI
+                        pnp 2e.b on  #  HW Monitor
+				 io 0x60 = 0x290
+                end
         end
 end
 
-#northbridge amd/amdk8
-#end
-#southbridge amd/amd8111 "amd8111"
-#end
-#mainboardinit archi386/smp/secondary.inc
-#superio NSC/pc87360
-#	register "com1" = "{1}"
-#	register "lpt" = "{1}"
-#end
 dir /pc80
-##dir /src/superio/winbond/w83627hf
 #dir /bioscall
-#dir /cpu/k8
 cpu k8 "cpu0"
   register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
 end