diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-10-08 07:43:09 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-10-08 07:43:09 +0000 |
commit | 5726f92027c4299a7cad46c9153dbe55543efb5e (patch) | |
tree | 3b48da7bf4d3c522769628e36e0b5df329188164 /src/mainboard/tyan/s2735 | |
parent | b97ee05dc72c52fbb694326863b4977736d0f225 (diff) |
Kconfig: AMD Fam10, all Tyan boards.
Fam10 doesn't build due to size constraints at this time.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2735')
-rw-r--r-- | src/mainboard/tyan/s2735/Kconfig | 62 | ||||
-rw-r--r-- | src/mainboard/tyan/s2735/Makefile.inc | 66 |
2 files changed, 128 insertions, 0 deletions
diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig new file mode 100644 index 0000000000..e39c5ea98a --- /dev/null +++ b/src/mainboard/tyan/s2735/Kconfig @@ -0,0 +1,62 @@ +config BOARD_TYAN_S2735 + bool "S2735" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7501 + select SOUTHBRIDGE_INTEL_I82870 + select SOUTHBRIDGE_INTEL_I82801ER + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select HAVE_OPTION_TABLE + select USE_DCACHE_RAM + +config MAINBOARD_DIR + string + default tyan/s2735 + depends on BOARD_TYAN_S2735 + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_TYAN_S2735 + +config DCACHE_RAM_SIZE + hex + default 0x1000 + depends on BOARD_TYAN_S2735 + +config LB_CKS_RANGE_START + int + default 49 + depends on BOARD_TYAN_S2735 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2735 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2735 + +config MAINBOARD_PART_NUMBER + string + default "S2735" + depends on BOARD_TYAN_S2735 + +config IRQ_SLOT_COUNT + int + default 15 + depends on BOARD_TYAN_S2735 + +config MAX_CPUS + int + default 4 + depends on BOARD_TYAN_S2735 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_TYAN_S2735 diff --git a/src/mainboard/tyan/s2735/Makefile.inc b/src/mainboard/tyan/s2735/Makefile.inc new file mode 100644 index 0000000000..0d3f8965e8 --- /dev/null +++ b/src/mainboard/tyan/s2735/Makefile.inc @@ -0,0 +1,66 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +driver-y += mainboard.o + +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +#driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds +ldscript-y += ../../../../src/cpu/x86/car/cache_as_ram.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + |