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authorarch import user (historical) <svn@openbios.org>2005-07-06 17:17:25 +0000
committerarch import user (historical) <svn@openbios.org>2005-07-06 17:17:25 +0000
commit6ca7636c8f52560e732cdd5b1c7829cda5aa2bde (patch)
treecc45ae7c4dea6e2c5338f52b4314106bf07023be /src/mainboard/tyan/s2735
parentb2ed53dd5669c2c3839633bd2b3b4af709a5b149 (diff)
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2735')
-rw-r--r--src/mainboard/tyan/s2735/Config.lb161
-rw-r--r--src/mainboard/tyan/s2735/Options.lb73
-rw-r--r--src/mainboard/tyan/s2735/auto.c20
-rw-r--r--src/mainboard/tyan/s2735/cache_as_ram_auto.c343
4 files changed, 523 insertions, 74 deletions
diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb
index 6ce12ebfd3..37d6493e74 100644
--- a/src/mainboard/tyan/s2735/Config.lb
+++ b/src/mainboard/tyan/s2735/Config.lb
@@ -16,6 +16,7 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@@ -34,6 +35,7 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end
+
##
## Build the objects we have code for in this directory.
##
@@ -42,7 +44,26 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+end
+
+else
+makerule ./auto.inc
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
##
## Romcc output
@@ -66,13 +87,24 @@ makerule ./auto.inc
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
+end
+
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
+if USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ ldscript /cpu/x86/32bit/entry32.lds
+ end
+
+ if CONFIG_USE_INIT
+ ldscript /cpu/intel/car/cache_as_ram.lds
+ end
+end
+
##
## Build our reset vector (This is where linuxBIOS is entered)
@@ -85,8 +117,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
+if USE_DCACHE_RAM
+else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
+end
##
## Include an id string (For safe flashing)
@@ -94,23 +129,40 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/intel/car/cache_as_ram.inc
+end
+
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover.lds
+else
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
##
## Setup RAM
##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+# ROMCC
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
@@ -118,15 +170,16 @@ mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
+end
+
##
## Include the secondary Configuration files
##
-dir /pc80
-
if CONFIG_CHIP_NAME
config chip.h
end
+
# sample config for tyan/s2735
chip northbridge/intel/e7501
device pci_domain 0 on
@@ -135,7 +188,12 @@ chip northbridge/intel/e7501
device pci 2.0 on
chip southbridge/intel/i82870
device pci 1c.0 on end
- device pci 1d.0 on end
+ device pci 1d.0 on
+ chip drivers/pci/onboard
+ device pci 1.0 on end # intel lan
+ device pci 1.1 on end
+ end
+ end
device pci 1e.0 on end
device pci 1f.0 on end
end
@@ -147,42 +205,55 @@ chip northbridge/intel/e7501
device pci 1d.2 on end
device pci 1d.3 on end
device pci 1d.7 on end
- device pci 1e.0 on end
+ device pci 1e.0 on
+ chip drivers/pci/onboard
+ device pci 1.0 on end # intel lan 10/100
+ end
+ chip drivers/pci/onboard
+ device pci 2.0 on end # ati
+ end
+ end
device pci 1f.0 on
- # device pci 8.0 end
- chip superio/winbond/w83627hf
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off end # CIR
- device pnp 2e.7 off end # GAME_MIDI_GIPO1
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
end
device pci 1f.1 off end
device pci 1f.2 on end
diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb
index 98c7e50f4f..16b23a66bd 100644
--- a/src/mainboard/tyan/s2735/Options.lb
+++ b/src/mainboard/tyan/s2735/Options.lb
@@ -9,7 +9,9 @@ uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
+uses SERIAL_CPU_INIT
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
@@ -33,8 +35,15 @@ uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@@ -44,31 +53,35 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses OBJCOPY
uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
-###
-### Build options
-###
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses CONFIG_USE_INIT
-##
## ROM_SIZE is the size of boot ROM that this board will use.
-#512K bytes
-#default ROM_SIZE=524288
+#512K bytes
+default ROM_SIZE=524288
#1M bytes
-default ROM_SIZE=1048576
+#default ROM_SIZE=1048576
+
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
default FALLBACK_SIZE=131072
+###
+### Build options
+###
+
##
## Build code for the fallback boot
##
@@ -79,23 +92,21 @@ default HAVE_FALLBACK_BOOT=1
##
default HAVE_HARD_RESET=1
-##
-## Funky hard reset implementation
-##
-#default HARD_RESET_BUS=3
-#default HARD_RESET_DEVICE=4
-#default HARD_RESET_FUNCTION=0
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
## Delay timer options
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=15
+default IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
@@ -121,8 +132,28 @@ default LB_CKS_LOC=123
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
+default SERIAL_CPU_INIT=0
+
+#BTEXT Console
+#default CONFIG_CONSOLE_BTEXT=1
+
+#VGA Console
+#default CONFIG_CONSOLE_VGA=1
+#default CONFIG_PCI_ROM_RUN=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xF2000000
+#default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+#default CONFIG_USE_INIT=1
+
+
##
## Build code to setup a generic IOAPIC
##
@@ -131,8 +162,10 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="Tyan"
-default MAINBOARD_VENDOR="s2735"
+default MAINBOARD_PART_NUMBER="s2735"
+default MAINBOARD_VENDOR="Tyan"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735
###
### LinuxBIOS layout values
diff --git a/src/mainboard/tyan/s2735/auto.c b/src/mainboard/tyan/s2735/auto.c
index 5874d5ea35..9cf5e50187 100644
--- a/src/mainboard/tyan/s2735/auto.c
+++ b/src/mainboard/tyan/s2735/auto.c
@@ -10,7 +10,9 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
+
#include "arch/i386/lib/console.c"
+
#include "ram/ramtest.c"
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
@@ -51,6 +53,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
+
#include "northbridge/intel/e7501/raminit.c"
#include "northbridge/intel/e7501/reset_test.c"
#include "sdram/generic_sdram.c"
@@ -87,7 +90,7 @@ static void main(unsigned long bist)
#endif
if(!bios_reset_detected()) {
enable_smbus();
-#if 1
+#if 0
dump_spd_registers(&memctrl[0]);
// dump_smbus_registers();
#endif
@@ -126,17 +129,16 @@ static void main(unsigned long bist)
print_debug_hex32(msr.lo);
print_debug("\r\n");
#endif
-/*
-#if 0
+
+#if 0
ram_check(0x00000000, msr.lo+(msr.hi<<32));
-#else
-#if 1
+#endif
+
+#if 0
// Check 16MB of memory @ 0
ram_check(0x00000000, 0x01000000);
-#else
// Check 16MB of memory @ 2GB
- ram_check(0x80000000, 0x81000000);
-#endif
+// ram_check(0x80000000, 0x81000000);
#endif
-*/
+
}
diff --git a/src/mainboard/tyan/s2735/cache_as_ram_auto.c b/src/mainboard/tyan/s2735/cache_as_ram_auto.c
new file mode 100644
index 0000000000..ebfc647d10
--- /dev/null
+++ b/src/mainboard/tyan/s2735/cache_as_ram_auto.c
@@ -0,0 +1,343 @@
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+
+#if 0
+static void post_code(uint8_t value) {
+#if 1
+ int i;
+ for(i=0;i<0x80000;i++) {
+ outb(value, 0x80);
+ }
+#endif
+}
+#endif
+
+#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
+#include "northbridge/intel/e7501/raminit.h"
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/intel/e7501/debug.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+static void hard_reset(void)
+{
+ /* full reset */
+ outb(0x0a, 0x0cf9);
+ outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+#if 1
+ /* link reset */
+ outb(0x02, 0x0cf9);
+ outb(0x06, 0x0cf9);
+#endif
+}
+
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ /* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+
+#include "northbridge/intel/e7501/raminit.c"
+#include "northbridge/intel/e7501/reset_test.c"
+#include "sdram/generic_sdram.c"
+
+
+#include "cpu/intel/car/copy_and_run.c"
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "southbridge/intel/i82801er/cmos_failover.c"
+
+void real_main(unsigned long bist);
+
+void amd64_main(unsigned long bist)
+{
+#if 1
+#if 0
+ unsigned cmos_result;
+ int i;
+ for(i=0;i<2;i++) {
+ cmos_result = cmos_read(0x10);
+ outb(cmos_result, 0x80);
+ }
+#endif
+__asm__ volatile (
+ "movl $(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-4), %esi\n\t"
+// "movl $(DCACHE_RAM_SIZE>>2), %ecx\n\t"
+ "movl $8, %ecx\n\t"
+".yin1x:\n\t"
+ "movl %esi, %eax\n\t"
+
+ "movl $0x2000, %edx\n\t"
+ "movb %ah, %al\n\t"
+".testy1:\n\t"
+ "outb %al, $0x80\n\t"
+ "decl %edx\n\t"
+ "jnz .testy1\n\t"
+
+ "movl (%esi), %eax\n\t"
+ "cmpb 0xff, %al\n\t"
+ "je .yin2\n\t"
+
+ "movl $0x2000, %edx\n\t"
+".testy2:\n\t"
+ "outb %al, $0x80\n\t"
+ "decl %edx\n\t"
+ "jnz .testy2\n\t"
+
+".yin2: decl %ecx\n\t"
+ "je .yout1x\n\t"
+ "sub $4, %esi\n\t"
+ "jmp .yin1x\n\t"
+".yout1x:\n\t"
+);
+#endif
+ /* Is this a deliberate reset by the bios */
+// post_code(0x22);
+ if (bios_reset_detected() && last_boot_normal()) {
+ goto normal_image;
+ }
+ /* This is the primary cpu how should I boot? */
+ else {
+ check_cmos_failed();
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ }
+ normal_image:
+// post_code(0x23);
+ __asm__ volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ );
+ cpu_reset:
+// post_code(0x24);
+#if 0
+ //CPU reset will reset memtroller ???
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ );
+#endif
+
+ fallback_image:
+// post_code(0x25);
+ real_main(bist);
+}
+void real_main(unsigned long bist)
+#else
+void amd64_main(unsigned long bist)
+#endif
+{
+ static const struct mem_controller memctrl[] = {
+ {
+ .d0 = PCI_DEV(0, 0, 0),
+ .d0f1 = PCI_DEV(0, 0, 1),
+ .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
+ .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
+ },
+ };
+
+ unsigned cpu_reset = 0;
+#if 1
+__asm__ volatile (
+ "movl $(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-4), %esi\n\t"
+// "movl $(DCACHE_RAM_SIZE>>2), %ecx\n\t"
+ "movl $8, %ecx\n\t"
+".zin1x:\n\t"
+ "movl %esi, %eax\n\t"
+
+ "movl $0x2000, %edx\n\t"
+ "movb %ah, %al\n\t"
+".testz1:\n\t"
+ "outb %al, $0x80\n\t"
+ "decl %edx\n\t"
+ "jnz .testz1\n\t"
+
+ "movl (%esi), %eax\n\t"
+ "cmpb 0xff, %al\n\t"
+ "je .zin2\n\t"
+
+ "movl $0x2000, %edx\n\t"
+".testz2:\n\t"
+ "outb %al, $0x80\n\t"
+ "decl %edx\n\t"
+ "jnz .testz2\n\t"
+
+".zin2: decl %ecx\n\t"
+ "je .zout1x\n\t"
+ "sub $4, %esi\n\t"
+ "jmp .zin1x\n\t"
+".zout1x:\n\t"
+);
+#endif
+
+ if (bist == 0)
+ {
+// early_mtrr_init();
+ enable_lapic();
+
+ }
+
+// post_code(0x32);
+
+ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+// setup_s2735_resource_map();
+
+ if(bios_reset_detected()) {
+ cpu_reset = 1;
+ goto cpu_reset_x;
+ }
+
+ enable_smbus();
+#if 0
+ dump_spd_registers(&memctrl[0]);
+#endif
+#if 0
+ dump_smbus_registers();
+#endif
+
+ memreset_setup();
+ sdram_initialize(1, memctrl);
+
+#if 0
+ dump_pci_devices();
+#endif
+
+#if 1
+ dump_pci_device(PCI_DEV(0, 0, 0));
+#endif
+
+
+#if 1
+ {
+ /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+ unsigned v_esp;
+ __asm__ volatile (
+ "movl %%esp, %0\n\t"
+ : "=a" (v_esp)
+ );
+#if CONFIG_USE_INIT
+ printk_debug("v_esp=%08x\r\n", v_esp);
+#else
+ print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
+#endif
+ }
+
+#endif
+#if 1
+
+cpu_reset_x:
+
+#if CONFIG_USE_INIT
+ printk_debug("cpu_reset = %08x\r\n",cpu_reset);
+#else
+ print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
+#endif
+
+ if(cpu_reset == 0) {
+ print_debug("Clearing initial memory region: ");
+ }
+ print_debug("No cache as ram now - ");
+
+ /* store cpu_reset to ebx */
+ __asm__ volatile (
+ "movl %0, %%ebx\n\t"
+ ::"a" (cpu_reset)
+ );
+
+ if(cpu_reset==0) {
+#define CLEAR_FIRST_1M_RAM 1
+#include "cpu/intel/car/cache_as_ram_post.c"
+ }
+ else {
+#undef CLEAR_FIRST_1M_RAM
+#include "cpu/intel/car/cache_as_ram_post.c"
+ }
+
+ __asm__ volatile (
+ /* set new esp */ /* before _RAMBASE */
+ "movl %0, %%ebp\n\t"
+ "movl %0, %%esp\n\t"
+ ::"a"( _RAMBASE - 4 )
+ );
+
+ {
+ unsigned new_cpu_reset;
+
+ /* get back cpu_reset from ebx */
+ __asm__ volatile (
+ "movl %%ebx, %0\n\t"
+ :"=a" (new_cpu_reset)
+ );
+
+ /* We can not go back any more, we lost old stack data in cache as ram*/
+ if(new_cpu_reset==0) {
+ print_debug("Use Ram as Stack now - done\r\n");
+ } else
+ {
+ print_debug("Use Ram as Stack now - \r\n");
+ }
+#if CONFIG_USE_INIT
+ printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
+#else
+ print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
+#endif
+
+ /*copy and execute linuxbios_ram */
+ copy_and_run(new_cpu_reset);
+ /* We will not return */
+ }
+#endif
+
+
+ print_debug("should not be here -\r\n");
+
+}