Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51

Creator:  Yinghai Lu <yhlu@tyan.com>

cache_as_ram for AMD and some intel


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 116 insertions, 45 deletions

diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb
index 6ce12ebfd3..37d6493e74 100644
--- a/src/mainboard/tyan/s2735/Config.lb
+++ b/src/mainboard/tyan/s2735/Config.lb
@@ -16,6 +16,7 @@ end
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_STREAM     = 1
 
 ##
 ## Compute where this copy of linuxBIOS will start in the boot rom
@@ -34,6 +35,7 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
 
 arch i386 end 
 
+
 ##
 ## Build the objects we have code for in this directory.
 ##
@@ -42,7 +44,26 @@ driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+end
+
+else
 
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
 
 ##
 ## Romcc output
@@ -66,13 +87,24 @@ makerule ./auto.inc
         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
+end
+
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript      /cpu/intel/car/cache_as_ram.lds
+        end
+end
+
 
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
@@ -85,8 +117,11 @@ else
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
+if USE_DCACHE_RAM
+else
 ### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
+end
 
 ##
 ## Include an id string (For safe flashing)
@@ -94,23 +129,40 @@ mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/intel/car/cache_as_ram.inc
+end
+
 ###
 ### This is the early phase of linuxBIOS startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+        mainboardinit ./failover.inc
+end
 end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
 
 ##
 ## Setup RAM
 ##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+# ROMCC
 mainboardinit cpu/x86/fpu/enable_fpu.inc
 mainboardinit cpu/x86/mmx/enable_mmx.inc
 mainboardinit cpu/x86/sse/enable_sse.inc
@@ -118,15 +170,16 @@ mainboardinit ./auto.inc
 mainboardinit cpu/x86/sse/disable_sse.inc
 mainboardinit cpu/x86/mmx/disable_mmx.inc
 
+end
+
 ##
 ## Include the secondary Configuration files 
 ##
-dir /pc80
-
 if CONFIG_CHIP_NAME
 	config chip.h
 end
 
+
 # sample config for tyan/s2735
 chip northbridge/intel/e7501
         device pci_domain 0 on
@@ -135,7 +188,12 @@ chip northbridge/intel/e7501
         	device pci 2.0 on
         		chip southbridge/intel/i82870
         	        	device pci 1c.0 on end
-		                device pci 1d.0 on end
+		                device pci 1d.0 on 
+					chip drivers/pci/onboard
+                                        	device pci 1.0 on end # intel lan
+                                                device pci 1.1 on end
+                                        end
+				end
         	                device pci 1e.0 on end
         	                device pci 1f.0 on end
         		end
@@ -147,42 +205,55 @@ chip northbridge/intel/e7501
         	        device pci 1d.2 on end
         	        device pci 1d.3 on end
 		        device pci 1d.7 on end
-		        device pci 1e.0 on end
+		        device pci 1e.0 on 
+                        	chip drivers/pci/onboard
+                                	device pci 1.0 on end # intel lan 10/100
+                                end
+                                chip drivers/pci/onboard
+                                        device pci 2.0 on end # ati 
+                                end
+			end
 		        device pci 1f.0 on
-        	        # device pci 8.0 end
-        	                chip superio/winbond/w83627hf
-        	                        device pnp 2e.0 on     #  Floppy
-        		                         io 0x60 = 0x3f0
-        	        	                irq 0x70 = 6
-        	                	        drq 0x74 = 2
-		                        end
-        	                        device pnp 2e.1 off     #  Parallel Port
-        	                                 io 0x60 = 0x378
-        		                        irq 0x70 = 7
-        	        	        end
-		                        device pnp 2e.2 on      #  Com1
-        	                                 io 0x60 = 0x3f8
-        	                                irq 0x70 = 4
-        		                end
-        	        	        device pnp 2e.3 off     #  Com2
-		                                 io 0x60 = 0x2f8
-        	                                irq 0x70 = 3
-        	                        end
-        		                device pnp 2e.5 on      #  Keyboard
-		                                 io 0x60 = 0x60
-        	                                 io 0x62 = 0x64
-        	                                irq 0x70 = 1
-        		                        irq 0x72 = 12
-        	        	        end
-		                        device pnp 2e.6 off end #  CIR
-        	                        device pnp 2e.7 off end #  GAME_MIDI_GIPO1
-        	                        device pnp 2e.8 off end #  GPIO2
-        		                device pnp 2e.9 off end #  GPIO3
-        	        	        device pnp 2e.a off end #  ACPI
-		                        device pnp 2e.b on      #  HW Monitor
-        	                                 io 0x60 = 0x290
-        	                        end
-        		        end
+				chip superio/winbond/w83627hf
+                                	device pnp 2e.0 on #  Floppy
+                                        	io 0x60 = 0x3f0
+                                                irq 0x70 = 6
+                                                drq 0x74 = 2
+                                        end
+	                                device pnp 2e.1 off #  Parallel Port
+                                                io 0x60 = 0x378
+                                                irq 0x70 = 7
+                                        end
+                                        device pnp 2e.2 on #  Com1
+        	                                io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+                                        end
+                                        device pnp 2e.3 on #  Com2
+                                                io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+                                        end
+                                        device pnp 2e.5 on #  Keyboard
+                                                io 0x60 = 0x60
+                                                io 0x62 = 0x64
+                                                irq 0x70 = 1
+                                                irq 0x72 = 12
+                                        end
+                                        device pnp 2e.6 off #  CIR
+                                                io 0x60 = 0x100
+                                        end
+                                        device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                                                io 0x60 = 0x220
+                                                io 0x62 = 0x300
+                                                irq 0x70 = 9
+                                        end                               
+                                        device pnp 2e.8 off end #  GPIO2
+                                        device pnp 2e.9 off end #  GPIO3
+                                        device pnp 2e.a off end #  ACPI
+                                        device pnp 2e.b on #  HW Monitor
+                                                io 0x60 = 0x290
+                                                irq 0x70 = 5
+                                        end
+				end
 		        end
 		        device pci 1f.1 off end
         	        device pci 1f.2 on end