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| author | Greg Watson <jarrah@users.sourceforge.net> | 2004-01-13 22:18:03 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2004-01-13 22:18:03 +0000 |
| commit | 6ff2ab96495c3128fc4adebd6a3affe294036fe7 (patch) | |
| tree | 46c351704d14202fd6110467d70ee715fdd20ba6 /src/mainboard/totalimpact/briq/Config.lb | |
| parent | 24aa3c8cf1de47c2732c73c4450417b8c79cf2c6 (diff) | |
*** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/totalimpact/briq/Config.lb')
| -rw-r--r-- | src/mainboard/totalimpact/briq/Config.lb | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb new file mode 100644 index 0000000000..b59f873c6b --- /dev/null +++ b/src/mainboard/totalimpact/briq/Config.lb @@ -0,0 +1,46 @@ +## +## Config file for the Total Impact briQ +## + +uses PCIC0_CFGADDR +uses PCIC0_CFGDATA +uses UART0_IO_BASE +uses CONFIG_BRIQ_750FX +uses CONFIG_BRIQ_7400 + +## +## Set PCI registers +## +default PCIC0_CFGADDR=0xeec00000 +default PCIC0_CFGDATA=0xeec00004 + +## +## Set UART base address +## +default UART0_IO_BASE=0xef600300 + +## +## Early board initialization, called from ppc_main() +## +initobject init.c +driver pci_bridge.c + +arch ppc end + +if CONFIG_BRIQ_750FX + cpu ppc/ppc7xx end +end +if CONFIG_BRIQ_7400 + cpu ppc/mpc74xx end +end + +## +## Include the secondary Configuration files +## +southbridge winbond/w83c553 end + +## +## Build the objects we have code for in this directory. +## + +addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a" |