summaryrefslogtreecommitdiff
path: root/src/mainboard/ti/beaglebone/devicetree.cb
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2020-07-29 11:01:26 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-08-05 07:27:38 +0000
commit239272e43de7eab15031b8fd3727596d3a23ee82 (patch)
tree95a403c5a6882f7adfa62a39aa62ecd45f6578e3 /src/mainboard/ti/beaglebone/devicetree.cb
parente58c6f5dfa9cf626c3164364677bcbc6cf5506fc (diff)
src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource
Ideally don't need to mark the entire top_of_ram till TOLUD range (used for stolen memory like GFX and ME, PTT, DPR, PRMRR, TSEG etc) as cacheable for OS usage as coreboot already done with mpinit w/ smm relocation early. TEST=Able to build and boot ICL, TGL RVP. Without this CL : PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a With this CL : PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index 9 No changes observed with MTRRs snapshot. Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/ti/beaglebone/devicetree.cb')
0 files changed, 0 insertions, 0 deletions