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| author | Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> | 2024-08-16 10:24:18 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-24 12:59:31 +0000 |
| commit | abf34584dbfecdd74db36dd24f6008d1051a96a9 (patch) | |
| tree | ea87f2c2975420f01a877434c8cd8a268994d648 /src/mainboard/ti/beaglebone/ddr3.h | |
| parent | 228088ea5276ad6dbcd7b145c89afb7aa6b8b203 (diff) | |
soc/mediatek: Refactor MMU operation for L2C SRAM and DMA
Refactor mmu operation by
- moving mtk_soc_disable_l2c_sram to l2c_ops.c
- keeping mtk_soc_after_dram in mmu_cmops.c
Change-Id: I14bd8a82e0b5f8f00ce2b52e5aee918e130912d4
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83937
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/ti/beaglebone/ddr3.h')
0 files changed, 0 insertions, 0 deletions