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| author | Edwin Beasant <edwin_beasant@virtensys.com> | 2010-01-26 11:22:43 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-01-26 11:22:43 +0000 |
| commit | a9796ed362f0d2b80f6c4e59c94db5d564324ebb (patch) | |
| tree | ff2eb71b69a93badce5d8b9e6d2933446d0a335b /src/mainboard/thomson/ip1000/Config.lb | |
| parent | e8d943f2668ab25d98ed61cd10d68353c4915f4b (diff) | |
- Clean up and comment writing of MSRs for cache control (Backport from v3)
- Invalidate Cache Tags (by means of in-place rewrite of cache data) which allows CAR data to be flushed to RAM
- Re-enable cache after flush of CAR to RAM
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/thomson/ip1000/Config.lb')
0 files changed, 0 insertions, 0 deletions