src/mainboard/lenovo-winent: Add space around operators

Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

7 files changed, 44 insertions, 44 deletions

diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c
index f9768b20bd..b397f52aea 100644
--- a/src/mainboard/technexion/tim5690/fadt.c
+++ b/src/mainboard/technexion/tim5690/fadt.c
@@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	fadt->firmware_ctrl = (u32) facs;
 	fadt->dsdt = (u32) dsdt;
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
@@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
 	pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
 
-	pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+	pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
 					* the contents of the PM registers at
 					* index 20-2B to decode ACPI I/O address.
 					* AcpiSmiEn & SmiCmdEn*/
-	pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
 	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
 
 	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 39192b071c..8895163651 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
 			dword = pci_read_config32(dev, 0xac);
 			dword &= ~(7 << 26);
 			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
 			/*
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index b94b06c416..e534617e4d 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	cpuid1 = cpuid(0x80000007);
 	if ((cpuid1.edx & 0x6) == 0x6) {
 		/* Read FIDVID_STATUS */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
@@ -124,7 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_fidvid_bsp(bsp_apicid);
 
 		/* show final fid and vid */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 	} else {
 		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
diff --git a/src/mainboard/technexion/tim5690/tn_post_code.c b/src/mainboard/technexion/tim5690/tn_post_code.c
index 1fa49355a4..213034a316 100644
--- a/src/mainboard/technexion/tim5690/tn_post_code.c
+++ b/src/mainboard/technexion/tim5690/tn_post_code.c
@@ -36,7 +36,7 @@
 void technexion_post_code_init(void)
 {
    uint8_t reg8_data;
-   device_t dev=0;
+   device_t dev = 0;
 
    // SMBus Module and ACPI Block (Device 20, Function 0)
    dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0);
@@ -44,80 +44,80 @@ void technexion_post_code_init(void)
    // LED[bit0]:GPIO0
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pmio_read(0x60);
-   reg8_data |= (1<<7);  // 1: GPIO if not used by SATA
+   reg8_data |= (1 << 7);  // 1: GPIO if not used by SATA
    pmio_write(0x60, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0x80);
-   reg8_data = ((reg8_data | (1<<0)) & ~(1<<4));
+   reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 4));
    pci_write_config8(dev, 0x80, reg8_data);
 
    // LED[bit1]:GPIO1
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pci_read_config8(dev, 0x80);
-   reg8_data = ((reg8_data | (1<<1)) & ~(1<<5));
+   reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5));
    pci_write_config8(dev, 0x80, reg8_data);
 
    // LED[bit2]:GPIO4
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pmio_read(0x5e);
-   reg8_data &= ~(1<<7); // 0: GPIO if not used by SATA
+   reg8_data &= ~(1 << 7); // 0: GPIO if not used by SATA
    pmio_write(0x5e, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<0);
+   reg8_data |= (1 << 0);
    pci_write_config8(dev, 0xa8, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<0);
+   reg8_data &= ~(1 << 0);
    pci_write_config8(dev, 0xa9, reg8_data);
 
    // LED[bit3]:GPIO6
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pmio_read(0x60);
-   reg8_data |= (1<<7); // 1: GPIO if not used by SATA
+   reg8_data |= (1 << 7); // 1: GPIO if not used by SATA
    pmio_write(0x60, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<2);
+   reg8_data |= (1 << 2);
    pci_write_config8(dev, 0xa8, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<2);
+   reg8_data &= ~(1 << 2);
    pci_write_config8(dev, 0xa9, reg8_data);
    // LED[bit4]:GPIO7
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<3);
+   reg8_data |= (1 << 3);
    pci_write_config8(dev, 0xa8, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<3);
+   reg8_data &= ~(1 << 3);
    pci_write_config8(dev, 0xa9, reg8_data);
 
    // LED[bit5]:GPIO8
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<4);
+   reg8_data |= (1 << 4);
    pci_write_config8(dev, 0xa8, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<4);
+   reg8_data &= ~(1 << 4);
    pci_write_config8(dev, 0xa9, reg8_data);
 
    // LED[bit6]:GPIO10
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pci_read_config8(dev, 0xab);
-   reg8_data = ((reg8_data | (1<<0)) & ~(1<<1));
+   reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 1));
    pci_write_config8(dev, 0xab, reg8_data);
 
    // LED[bit7]:GPIO66
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pmio_read(0x68);
-   reg8_data &= ~(1<<5); // 0: GPIO
+   reg8_data &= ~(1 << 5); // 0: GPIO
    pmio_write(0x68, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0x7e);
-   reg8_data = ((reg8_data | (1<<1)) & ~(1<<5));
+   reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5));
    pci_write_config8(dev, 0x7e, reg8_data);
 
 }
@@ -129,7 +129,7 @@ void technexion_post_code_init(void)
 void technexion_post_code(uint8_t udata8)
 {
    uint8_t u8_data;
-   device_t dev=0;
+   device_t dev = 0;
 
    // SMBus Module and ACPI Block (Device 20, Function 0)
 #ifdef __PRE_RAM__
@@ -143,80 +143,80 @@ void technexion_post_code(uint8_t udata8)
    // LED[bit0]:GPIO0
    u8_data = pci_read_config8(dev, 0x80);
    if (udata8 & 0x1) {
-      u8_data |= (1<<0);
+      u8_data |= (1 << 0);
    }
    else {
-      u8_data &= ~(1<<0);
+      u8_data &= ~(1 << 0);
    }
    pci_write_config8(dev, 0x80, u8_data);
 
    // LED[bit1]:GPIO1
    u8_data = pci_read_config8(dev, 0x80);
    if (udata8 & 0x2) {
-      u8_data |= (1<<1);
+      u8_data |= (1 << 1);
    }
    else {
-      u8_data &= ~(1<<1);
+      u8_data &= ~(1 << 1);
    }
    pci_write_config8(dev, 0x80, u8_data);
 
    // LED[bit2]:GPIO4
    u8_data = pci_read_config8(dev, 0xa8);
    if (udata8 & 0x4) {
-      u8_data |= (1<<0);
+      u8_data |= (1 << 0);
    }
    else {
-      u8_data &= ~(1<<0);
+      u8_data &= ~(1 << 0);
    }
    pci_write_config8(dev, 0xa8, u8_data);
 
    // LED[bit3]:GPIO6
    u8_data = pci_read_config8(dev, 0xa8);
    if (udata8 & 0x8) {
-      u8_data |= (1<<2);
+      u8_data |= (1 << 2);
    }
    else {
-      u8_data &= ~(1<<2);
+      u8_data &= ~(1 << 2);
    }
    pci_write_config8(dev, 0xa8, u8_data);
 
    // LED[bit4]:GPIO7
    u8_data = pci_read_config8(dev, 0xa8);
    if (udata8 & 0x10) {
-      u8_data |= (1<<3);
+      u8_data |= (1 << 3);
    }
    else {
-      u8_data &= ~(1<<3);
+      u8_data &= ~(1 << 3);
    }
    pci_write_config8(dev, 0xa8, u8_data);
 
    // LED[bit5]:GPIO8
    u8_data = pci_read_config8(dev, 0xa8);
    if (udata8 & 0x20) {
-      u8_data |= (1<<4);
+      u8_data |= (1 << 4);
    }
    else {
-      u8_data &= ~(1<<4);
+      u8_data &= ~(1 << 4);
    }
    pci_write_config8(dev, 0xa8, u8_data);
 
    // LED[bit6]:GPIO10
    u8_data = pci_read_config8(dev, 0xab);
    if (udata8 & 0x40) {
-      u8_data |= (1<<0);
+      u8_data |= (1 << 0);
    }
    else {
-      u8_data &= ~(1<<0);
+      u8_data &= ~(1 << 0);
    }
    pci_write_config8(dev, 0xab, u8_data);
 
    // LED[bit7]:GPIO66
    u8_data = pci_read_config8(dev, 0x7e);
    if (udata8 & 0x80) {
-      u8_data |= (1<<1);
+      u8_data |= (1 << 1);
    }
    else {
-      u8_data &= ~(1<<1);
+      u8_data &= ~(1 << 1);
    }
    pci_write_config8(dev, 0x7e, u8_data);
 
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index 939becfa78..9e1c58d29e 100644
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -59,7 +59,7 @@ static void enable_onboard_nic(void)
 	byte |= ( 1 << 7);
 	pci_write_config8(sm_dev, 0x9a, byte);
 
-	byte=pm_ioread(0x59);
+	byte = pm_ioread(0x59);
 	byte &= ~( 1<< 5);
 	pm_iowrite(0x59,byte);
 
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 39192b071c..8895163651 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
 			dword = pci_read_config32(dev, 0xac);
 			dword &= ~(7 << 26);
 			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
 			/*
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index e052d923a5..b1805a9d8f 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	cpuid1 = cpuid(0x80000007);
 	if ((cpuid1.edx & 0x6) == 0x6 ) {
 		/* Read FIDVID_STATUS */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
@@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_fidvid_bsp(bsp_apicid);
 
 		/* show final fid and vid */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 	} else {
 		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");