diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 00:04:22 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-31 03:41:11 +0000 |
| commit | 1740230ace3aeede3a7ee5cadd1e17744cda07b3 (patch) | |
| tree | bf4e9f45d71fef44056ba901ac91fcbfb423a525 /src/mainboard/technexion | |
| parent | f054a4bf3d6ce459d15c9375e4ca2390d04ffb68 (diff) | |
Remove all AMD K8 boards
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.
Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/technexion')
45 files changed, 0 insertions, 8337 deletions
diff --git a/src/mainboard/technexion/Kconfig b/src/mainboard/technexion/Kconfig deleted file mode 100644 index 163a4bfe6a..0000000000 --- a/src/mainboard/technexion/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if VENDOR_TECHNEXION - -choice - prompt "Mainboard model" - -source "src/mainboard/technexion/*/Kconfig.name" - -endchoice - -source "src/mainboard/technexion/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "Technexion" - -endif # VENDOR_TECHNEXION diff --git a/src/mainboard/technexion/Kconfig.name b/src/mainboard/technexion/Kconfig.name deleted file mode 100644 index 6366ff59b6..0000000000 --- a/src/mainboard/technexion/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_TECHNEXION - bool "Technexion" diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig deleted file mode 100644 index 0220d7762b..0000000000 --- a/src/mainboard/technexion/tim5690/Kconfig +++ /dev/null @@ -1,52 +0,0 @@ -if BOARD_TECHNEXION_TIM5690 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SOCKET_S1G1 - select NORTHBRIDGE_AMD_AMDK8 - select SOUTHBRIDGE_AMD_RS690 - select SOUTHBRIDGE_AMD_SB600 - select SUPERIO_ITE_IT8712F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select HAVE_ACPI_TABLES - select GFXUMA - select BOARD_ROMSIZE_KB_512 - select QRANK_DIMM_SUPPORT - select SET_FIDVID - -config MAINBOARD_DIR - string - default technexion/tim5690 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "TIM-5690" - -config MAX_CPUS - int - default 2 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_TECHNEXION_TIM5690 diff --git a/src/mainboard/technexion/tim5690/Kconfig.name b/src/mainboard/technexion/tim5690/Kconfig.name deleted file mode 100644 index 24aad25c2c..0000000000 --- a/src/mainboard/technexion/tim5690/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_TECHNEXION_TIM5690 - bool "TIM-5690" diff --git a/src/mainboard/technexion/tim5690/Makefile.inc b/src/mainboard/technexion/tim5690/Makefile.inc deleted file mode 100644 index 51202179f1..0000000000 --- a/src/mainboard/technexion/tim5690/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# Needed by irq_tables and mptable and acpi_tables. - -# This is debug message for products of Technexion. -ramstage-y += tn_post_code.c - -ramstage-y += speaker.c -ramstage-$(CONFIG_VGA_ROM_RUN) += vgabios.c diff --git a/src/mainboard/technexion/tim5690/acpi/ide.asl b/src/mainboard/technexion/tim5690/acpi/ide.asl deleted file mode 100644 index d5badfcb6b..0000000000 --- a/src/mainboard/technexion/tim5690/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/technexion/tim5690/acpi/routing.asl b/src/mainboard/technexion/tim5690/acpi/routing.asl deleted file mode 100644 index bcb14e7e37..0000000000 --- a/src/mainboard/technexion/tim5690/acpi/routing.asl +++ /dev/null @@ -1,254 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS690 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0012FFFF, 1, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 2, INTC, 0 }, - Package(){0x0013FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS690 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0012FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0013FFFF, 0, 0, 16 }, - Package(){0x0013FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 2, 0, 18 }, - Package(){0x0013FFFF, 3, 0, 19 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS690 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS690 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/technexion/tim5690/acpi/sata.asl b/src/mainboard/technexion/tim5690/acpi/sata.asl deleted file mode 100644 index 474e5ed6d2..0000000000 --- a/src/mainboard/technexion/tim5690/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00120000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/technexion/tim5690/acpi/usb.asl b/src/mainboard/technexion/tim5690/acpi/usb.asl deleted file mode 100644 index dbffa39ad2..0000000000 --- a/src/mainboard/technexion/tim5690/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -/* If (LLessEqual(UOM5,9)) { -* Scope (\_GPE) { -* Method (_L1A) { -* UCOC() -* if (LEqual(GPB5,PLC5)) { -* Not(PLC5,PLC5) -* Store(PLC5, \_SB.PT5D) -* } -* } -* } -* } -*/ - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/technexion/tim5690/acpi_tables.c b/src/mainboard/technexion/tim5690/acpi_tables.c deleted file mode 100644 index 75834b6c7f..0000000000 --- a/src/mainboard/technexion/tim5690/acpi_tables.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/amd/amdk8_sysconf.h> -#include "northbridge/amd/amdk8/acpi.h" -#include <arch/cpu.h> -#include <cpu/amd/powernow.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - get_bus_conf(); - - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB600 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/technexion/tim5690/board_info.txt b/src/mainboard/technexion/tim5690/board_info.txt deleted file mode 100644 index c63907ad01..0000000000 --- a/src/mainboard/technexion/tim5690/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: half -Board URL: http://www.technexion.com/index.php/embedded-mainboards/amd/tim-5690 diff --git a/src/mainboard/technexion/tim5690/cmos.layout b/src/mainboard/technexion/tim5690/cmos.layout deleted file mode 100644 index 104d51f4c2..0000000000 --- a/src/mainboard/technexion/tim5690/cmos.layout +++ /dev/null @@ -1,69 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb deleted file mode 100644 index bf462e213a..0000000000 --- a/src/mainboard/technexion/tim5690/devicetree.cb +++ /dev/null @@ -1,112 +0,0 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_S1G1 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x3050 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "1" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "0" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl deleted file mode 100644 index 44da647f8e..0000000000 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ /dev/null @@ -1,1674 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/amd/sb600/sb600.h> - -/* DefinitionBlock Statement */ -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "TECHNE", /* OEMID */ - "COREBOOT", /* TABLE ID */ - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve) - { - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - - Method(CIRQ, 0x00, NotSerialized) - { - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - //Method(_L03) { - // /* DBGO("\\_GPE\\_L00\n") */ - // Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - //} - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00120000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { /* HPET */ - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* HPET is visible */ - } - Method(_CRS, 0) { - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE IT8712F Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the IT8712F MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* IT8712F magic number */ - } - /* Exit the IT8712F MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - - /* - * Keyboard PME is routed to SB600 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("IT8712F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - //Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c deleted file mode 100644 index b397f52aea..0000000000 --- a/src/mainboard/technexion/tim5690/fadt.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - -#include <string.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <device/device.h> -#include "southbridge/amd/sb600/sb600.h" - -/*extern*/ u16 pm_base = 0x800; -/* pm_base should be set in sb ACPI */ -/* pm_base should be got from bar2 of rs690. Here I compact ACPI - * registers into 32 bytes limit. - * */ - -#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */ -#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */ -#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */ -#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */ - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - pm_base &= 0xFFFF; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - - /* Prepare the header */ - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; - /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - /* disable system management mode by setting to 0: */ - fadt->smi_cmd = 0; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; - - pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - - /* CpuControl is in \_PR.CP00, 6 bytes */ - pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); - pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); - - pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */ - - pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); - - pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 20-2B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ - pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alrm work */ - fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ - fadt->flags = 0x0001c1a5;/* 0x25; */ - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c deleted file mode 100644 index b1b7270802..0000000000 --- a/src/mainboard/technexion/tim5690/get_bus_conf.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <string.h> -#include <stdint.h> -#include <stdlib.h> -#include <cpu/amd/multicore.h> - -#include <cpu/amd/amdk8_sysconf.h> - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u8 bus_rs690[8]; -u8 bus_sb600[2]; -u32 apicid_sb600; - -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* -* HT Chain device num, actually it is unit id base of every ht device in chain, -* assume every chain only have 4 ht device at most -*/ -u32 hcdnx[] = { - 0x20202020, -}; - -u32 sbdn_rs690; -u32 sbdn_sb600; - - - -static u32 get_bus_conf_done = 0; - -void get_bus_conf(void) -{ - u32 apicid_base; - struct device *dev; - int i; - - if (get_bus_conf_done == 1) - return; /* do it only once */ - get_bus_conf_done = 1; - - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for (i = 0; i < sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } - - get_sblk_pci1234(); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - sbdn_rs690 = sysconf.sbdn; - sbdn_sb600 = 0; - - for (i = 0; i < 2; i++) { - bus_sb600[i] = 0; - } - for (i = 0; i < 8; i++) { - bus_rs690[i] = 0; - } - - bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb600[0] = bus_rs690[0]; - - /* sb600 */ - dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4)); - if (dev) { - bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - - /* rs690 */ - for (i = 1; i < 8; i++) { - dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0)); - if (dev) { - bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } - - /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb600 = apicid_base + 0; -} diff --git a/src/mainboard/technexion/tim5690/irq_tables.c b/src/mainboard/technexion/tim5690/irq_tables.c deleted file mode 100644 index 4c2a48dff7..0000000000 --- a/src/mainboard/technexion/tim5690/irq_tables.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -#include <cpu/amd/amdk8_sysconf.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -extern u8 bus_rs690[8]; -extern u8 bus_sb600[2]; -extern unsigned long sbdn_sb600; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = bus_sb600[0]; - pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4; - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4, - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c deleted file mode 100644 index 12050f07fa..0000000000 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <device/pci_def.h> -#include <southbridge/amd/sb600/sb600.h> -#include <superio/ite/it8712f/it8712f.h> -#include "tn_post_code.h" -#include "vgabios.h" - -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ -#define SMBUS_IO_BASE 0x1000 - - -/* Video BIOS Function Extensions Specification - */ -//Callback Sub-Function 00h - Get LCD Panel ID -#define LCD_PANEL_ID_NO 0x00 /* No LCD */ -#define LCD_PANEL_ID_01 0x01 /* 1024x768, 24 bits, 1 channel */ -#define LCD_PANEL_ID_02 0x02 /* 1280x1024, 24 bits, 2 channels */ -#define LCD_PANEL_ID_03 0x03 /* 1440x900, 24 bits, 2 channels */ -#define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */ -#define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */ -#define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */ -//Callback Sub-Function 05h - Select Boot-up TV Standard -#define TV_MODE_00 0x00 /* NTSC */ -#define TV_MODE_01 0x01 /* PAL */ -#define TV_MODE_02 0x02 /* PALM */ -#define TV_MODE_03 0x03 /* PAL60 */ -#define TV_MODE_04 0x04 /* NTSCJ */ -#define TV_MODE_05 0x05 /* PALCN */ -#define TV_MODE_06 0x06 /* PALN */ -#define TV_MODE_09 0x09 /* SCART-RGB */ -#define TV_MODE_NO 0xff /* No TV Support */ - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 - -/* Global configuration registers. */ -#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ -#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ - -#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ -#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */ - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) - - -/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) -{ - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8712f_enter_conf(void) -{ - /* Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8712F_CONFIGURATION_PORT); - outb(0x01, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); -} - -static void it8712f_exit_conf(void) -{ - /* Exit the configuration state (MB PnP mode). */ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); -} - -/* set thermal config - */ -static void set_thermal_config(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); - - /* sb600 settings for thermal config */ - /* set SB600 GPIO 64 to GPIO with pull-up */ - byte = pm2_ioread(0x42); - byte &= 0x3f; - pm2_iowrite(0x42, byte); - - /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x56); - word |= 1 << 7; - pci_write_config16(sm_dev, 0x56, word); - - /* set GPIO 64 internal pull-up */ - byte = pm2_ioread(0xf0); - byte &= 0xee; - pm2_iowrite(0xf0, byte); - - /* set Talert to be active low */ - byte = pm_ioread(0x67); - byte &= ~(1 << 5); - pm_iowrite(0x67, byte); - - /* set Talert to generate ACPI event */ - byte = pm_ioread(0x3c); - byte &= 0xf3; - pm_iowrite(0x3c, byte); - - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ -} - -/* Mainboard specific GPIO setup. */ -static void mb_gpio_init(u16 *iobase) -{ - /* Init Super I/O GPIOs. */ - it8712f_enter_conf(); - outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); - outb(IT8712F_GPIO, SIO_DATA); - outb(0x62, SIO_INDEX); - outb((*iobase >> 8), SIO_DATA); - outb(0x63, SIO_INDEX); - outb((*iobase & 0xff), SIO_DATA); - it8712f_exit_conf(); -} - -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) -/* The LCD's panel id seletion. */ -static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) -{ - switch (num_id) { - case 0x1: - vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_01; - break; - case 0x2: - vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_02; - break; - case 0x3: - vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_03; - break; - case 0x4: - vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_04; - break; - case 0x5: - vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_05; - break; - case 0x6: - vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_06; - break; - default: - vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_NO; - break; - } -} -#endif - -/************************************************* -* enable the dedicated function in tim5690 board. -* This function called early than rs690_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - u16 gpio_base = IT8712F_SIMPLE_IO_BASE; -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) - rs690_vbios_regs vbios_regs; - u8 port2; -#endif - - printk(BIOS_INFO, "Mainboard tim5690 Enable. dev=0x%p\n", dev); - - mb_gpio_init(&gpio_base); - -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) - /* The LCD's panel id seletion by switch. */ - port2 = inb(gpio_base+1); - lcd_panel_id(&vbios_regs, ((~port2) & 0xf)); - - /* No support TV */ - vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO; - vgabios_init(&vbios_regs); -#endif - - set_thermal_config(); -} - -void mainboard_post(u8 value) -{ - switch (value) { - case POST_ENTER_ELF_BOOT: - technexion_post_code(LED_MESSAGE_FINISH); - break; - } -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c deleted file mode 100644 index 9515931627..0000000000 --- a/src/mainboard/technexion/tim5690/mptable.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> -#include <arch/io.h> -#include <string.h> -#include <stdint.h> -#include <cpu/amd/amdk8_sysconf.h> - -extern u8 bus_rs690[8]; -extern u8 bus_sb600[2]; - -extern u32 apicid_sb600; - -extern u32 sbdn_rs690; -extern u32 sbdn_sb600; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - get_bus_conf(); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(bus_sb600[0], - PCI_DEVFN(sbdn_sb600 + 0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb600, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/technexion/tim5690/resourcemap.c b/src/mainboard/technexion/tim5690/resourcemap.c deleted file mode 100644 index a513616703..0000000000 --- a/src/mainboard/technexion/tim5690/resourcemap.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void setup_tim5690_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c deleted file mode 100644 index e3f40d1166..0000000000 --- a/src/mainboard/technexion/tim5690/romstage.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <cpu/amd/model_fxx_rev.h> -#include <northbridge/amd/amdk8/raminit.h> -#include <delay.h> -#include <spd.h> -#include <cpu/x86/lapic.h> - -#include <superio/ite/common/ite.h> -#include <superio/ite/it8712f/it8712f.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs690/early_setup.c" -#include "southbridge/amd/sb600/early_setup.c" - -#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) - -void memreset(int controllers, const struct mem_controller *ctrl) { } -void activate_spd_rom(const struct mem_controller *ctrl) { } - -int spd_read_byte(u32 device, u32 address) -{ - return smbus_read_byte(device, address); -} - -#include <northbridge/amd/amdk8/amdk8.h> -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "lib/generic_sdram.c" -#include "resourcemap.c" -#include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/model_fxx/init_cpus.c" -#include "cpu/amd/model_fxx/fidvid.c" -#include "tn_post_code.c" -#include "speaker.c" -#include "northbridge/amd/amdk8/early_ht.c" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; - int needs_reset = 0; - u32 bsp_apicid = 0; - msr_t msr; - struct cpuid_result cpuid1; - struct sys_info *sysinfo = &sysinfo_car; - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - } - - technexion_post_code_init(); - technexion_post_code(LED_MESSAGE_START); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - enable_rs690_dev8(); - sb600_lpc_init(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - ite_kill_watchdog(GPIO_DEV); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); - - setup_tim5690_resource_map(); - - setup_coherent_ht_domain(); - -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); - start_other_cores(); -#endif - wait_all_aps_started(bsp_apicid); - - ht_setup_chains_x(sysinfo); - - /* run _early_setup before soft-reset. */ - rs690_early_setup(); - sb600_early_setup(); - - /* Check to see if processor is capable of changing FIDVID */ - /* otherwise it will throw a GP# when reading FIDVID_STATUS */ - cpuid1 = cpuid(0x80000007); - if ((cpuid1.edx & 0x6) == 0x6) { - /* Read FIDVID_STATUS */ - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - - /* show final fid and vid */ - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - } else { - printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); - } - - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - rs690_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); - - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } - - speaker_init(255); - speaker_on_nodelay(); - - allow_all_aps_stop(bsp_apicid); - - /* It's the time to set ctrl now; */ - printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", - sysinfo->nodes, sysinfo->ctrl, spd_addr); - - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - technexion_post_code(LED_MESSAGE_RAM); - - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - - speaker_off_nodelay(); - - rs690_before_pci_init(); - sb600_before_pci_init(); -} diff --git a/src/mainboard/technexion/tim5690/speaker.c b/src/mainboard/technexion/tim5690/speaker.c deleted file mode 100644 index 7c0ea6492b..0000000000 --- a/src/mainboard/technexion/tim5690/speaker.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Libra Li <libra.li@technexion.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifdef __PRE_RAM__ - -#include <arch/cpu.h> -#include "southbridge/amd/sb600/sb600.h" - -#else - -#include <arch/io.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "southbridge/amd/sb600/sb600.h" -#include <delay.h> - -#endif /* __PRE_RAM__ */ - -#include "speaker.h" - -void speaker_init(uint8_t time) { - /* SB600 RRG. - * Options_0 - RW - 8 bits - [PM_Reg: 60h]. - * SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output. - */ -#ifdef __PRE_RAM__ - pmio_write(0x60, (pmio_read(0x60) | (1<<5))); -#else - pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5))); -#endif /* __PRE_RAM__ */ - - /* SB600 RRG. - * Tmr1CntrlWord - RW - 8 bits - [IO_Reg: 43h]. - * ModeSelect, bit[3:1]=011b, Square wave output. - * CmmandSelect, bit[5:4]=11b, Read/write least, and then most significant byte. - * CounterSelect, bit[7:6]=10b, Select counter 2. - */ - outb(0xb6, 0x43); - - - /* SB600 RRG. - * TimerCh2- RW - 8 bits - [IO_Reg: 42h]. - */ - outb(time, 0x42); -} - -void speaker_on_nodelay(void) { - /* SB600 RRG. - * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. - * SpkrEnable, bit[0]=1b, Enable counter 2 - * SpkrTmrEnable, bit[1]=1b, Speaker timer on - */ - outb(inb(0x61) | 0x03, 0x61); -} - -void speaker_on_delay(void) { - speaker_on_nodelay(); - mdelay(100); -} - -void speaker_off_nodelay(void) { - /* SB600 RRG. - * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. - * SpkrEnable, bit[0]=0b, Disable counter 2 - * SpkrTmrEnable, bit[1]=0b, Speaker timer off - */ - outb(inb(0x61) & ~0x03, 0x61); -} - -void speaker_off_delay(void) { - speaker_off_nodelay(); - mdelay(100); -} diff --git a/src/mainboard/technexion/tim5690/speaker.h b/src/mainboard/technexion/tim5690/speaker.h deleted file mode 100644 index bb544b0bce..0000000000 --- a/src/mainboard/technexion/tim5690/speaker.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Libra Li <libra.li@technexion.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -void speaker_init(uint8_t time); -void speaker_on_nodelay(void); -void speaker_off_nodelay(void); -void speaker_on_delay(void); -void speaker_off_delay(void); diff --git a/src/mainboard/technexion/tim5690/tn_post_code.c b/src/mainboard/technexion/tim5690/tn_post_code.c deleted file mode 100644 index 607c44664a..0000000000 --- a/src/mainboard/technexion/tim5690/tn_post_code.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Libra Li <libra.li@technexion.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifdef __PRE_RAM__ - -#include <arch/cpu.h> -#include "southbridge/amd/sb600/sb600.h" - -#else - -#include <device/pci.h> -#include <device/pci_ids.h> - -#endif - -#include "tn_post_code.h" - - -#ifdef __SIMPLE_DEVICE__ - -// TechNexion's Post Code Initially. -void technexion_post_code_init(void) -{ - uint8_t reg8_data; - pci_devfn_t dev = 0; - - // SMBus Module and ACPI Block (Device 20, Function 0) - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); - - // LED[bit0]:GPIO0 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pmio_read(0x60); - reg8_data |= (1 << 7); // 1: GPIO if not used by SATA - pmio_write(0x60, reg8_data); - - reg8_data = pci_read_config8(dev, 0x80); - reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 4)); - pci_write_config8(dev, 0x80, reg8_data); - - // LED[bit1]:GPIO1 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pci_read_config8(dev, 0x80); - reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5)); - pci_write_config8(dev, 0x80, reg8_data); - - // LED[bit2]:GPIO4 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pmio_read(0x5e); - reg8_data &= ~(1 << 7); // 0: GPIO if not used by SATA - pmio_write(0x5e, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1 << 0); - pci_write_config8(dev, 0xa8, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1 << 0); - pci_write_config8(dev, 0xa9, reg8_data); - - // LED[bit3]:GPIO6 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pmio_read(0x60); - reg8_data |= (1 << 7); // 1: GPIO if not used by SATA - pmio_write(0x60, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1 << 2); - pci_write_config8(dev, 0xa8, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1 << 2); - pci_write_config8(dev, 0xa9, reg8_data); - // LED[bit4]:GPIO7 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1 << 3); - pci_write_config8(dev, 0xa8, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1 << 3); - pci_write_config8(dev, 0xa9, reg8_data); - - // LED[bit5]:GPIO8 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1 << 4); - pci_write_config8(dev, 0xa8, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1 << 4); - pci_write_config8(dev, 0xa9, reg8_data); - - // LED[bit6]:GPIO10 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pci_read_config8(dev, 0xab); - reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 1)); - pci_write_config8(dev, 0xab, reg8_data); - - // LED[bit7]:GPIO66 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pmio_read(0x68); - reg8_data &= ~(1 << 5); // 0: GPIO - pmio_write(0x68, reg8_data); - - reg8_data = pci_read_config8(dev, 0x7e); - reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5)); - pci_write_config8(dev, 0x7e, reg8_data); - -} - -#endif - -/* TechNexion's Post Code. - */ -void technexion_post_code(uint8_t udata8) -{ - uint8_t u8_data; - - // SMBus Module and ACPI Block (Device 20, Function 0) -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = 0; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); -#else - struct device *dev = NULL; - dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0); -#endif - - udata8 = ~(udata8); - - // LED[bit0]:GPIO0 - u8_data = pci_read_config8(dev, 0x80); - if (udata8 & 0x1) { - u8_data |= (1 << 0); - } - else { - u8_data &= ~(1 << 0); - } - pci_write_config8(dev, 0x80, u8_data); - - // LED[bit1]:GPIO1 - u8_data = pci_read_config8(dev, 0x80); - if (udata8 & 0x2) { - u8_data |= (1 << 1); - } - else { - u8_data &= ~(1 << 1); - } - pci_write_config8(dev, 0x80, u8_data); - - // LED[bit2]:GPIO4 - u8_data = pci_read_config8(dev, 0xa8); - if (udata8 & 0x4) { - u8_data |= (1 << 0); - } - else { - u8_data &= ~(1 << 0); - } - pci_write_config8(dev, 0xa8, u8_data); - - // LED[bit3]:GPIO6 - u8_data = pci_read_config8(dev, 0xa8); - if (udata8 & 0x8) { - u8_data |= (1 << 2); - } - else { - u8_data &= ~(1 << 2); - } - pci_write_config8(dev, 0xa8, u8_data); - - // LED[bit4]:GPIO7 - u8_data = pci_read_config8(dev, 0xa8); - if (udata8 & 0x10) { - u8_data |= (1 << 3); - } - else { - u8_data &= ~(1 << 3); - } - pci_write_config8(dev, 0xa8, u8_data); - - // LED[bit5]:GPIO8 - u8_data = pci_read_config8(dev, 0xa8); - if (udata8 & 0x20) { - u8_data |= (1 << 4); - } - else { - u8_data &= ~(1 << 4); - } - pci_write_config8(dev, 0xa8, u8_data); - - // LED[bit6]:GPIO10 - u8_data = pci_read_config8(dev, 0xab); - if (udata8 & 0x40) { - u8_data |= (1 << 0); - } - else { - u8_data &= ~(1 << 0); - } - pci_write_config8(dev, 0xab, u8_data); - - // LED[bit7]:GPIO66 - u8_data = pci_read_config8(dev, 0x7e); - if (udata8 & 0x80) { - u8_data |= (1 << 1); - } - else { - u8_data &= ~(1 << 1); - } - pci_write_config8(dev, 0x7e, u8_data); - -} diff --git a/src/mainboard/technexion/tim5690/tn_post_code.h b/src/mainboard/technexion/tim5690/tn_post_code.h deleted file mode 100644 index e969ea83cc..0000000000 --- a/src/mainboard/technexion/tim5690/tn_post_code.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Libra Li <libra.li@technexion.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define LED_MESSAGE_START 0xFF -#define LED_MESSAGE_FINISH 0x99 -#define LED_MESSAGE_RAM 0x01 - - -#ifdef __PRE_RAM__ - -// TechNexion's Post Code Initially. -void technexion_post_code_init(void); - -#endif - -void technexion_post_code(uint8_t udata8); diff --git a/src/mainboard/technexion/tim5690/vgabios.c b/src/mainboard/technexion/tim5690/vgabios.c deleted file mode 100644 index fe4b41cde9..0000000000 --- a/src/mainboard/technexion/tim5690/vgabios.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2009 Libra Li <libra.li@technexion.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <console/console.h> -#include <arch/interrupt.h> -#include "vgabios.h" -#include <x86emu/regs.h> - - -int tim5690_int15_handler(void); - -static rs690_vbios_regs vbios_regs_local; - -/* Initialization interrupt function */ -static void vbios_fun_init(rs690_vbios_regs *vbios_regs) -{ - vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id; - vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard; -} - -/* BIOS int15 function */ -int tim5690_int15_handler(void) -{ - int res = 0; - - printk(BIOS_DEBUG, "tim5690_int15_handler\n"); - - switch (X86_EAX & 0xffff) { - case AMD_RS690_INT15: - switch (X86_EBX & 0xff) { - case 0x00: - X86_EAX &= ~(0xff); - X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun00_panel_id; - res = 1; - break; - case 0x05: - X86_EAX &= ~(0xff); - X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun05_tv_standard; - res = 1; - break; - } - break; - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - X86_EAX & 0xffff); - break; - } - - return res; -} - -/* Initialization VBIOS function */ -void vgabios_init(rs690_vbios_regs *vbios_regs) -{ - printk(BIOS_DEBUG, "vgabios_init\n"); - - mainboard_interrupt_handlers(0x15, &tim5690_int15_handler); - vbios_fun_init(vbios_regs); -} diff --git a/src/mainboard/technexion/tim5690/vgabios.h b/src/mainboard/technexion/tim5690/vgabios.h deleted file mode 100644 index f6ad63e7a5..0000000000 --- a/src/mainboard/technexion/tim5690/vgabios.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2009 Libra Li <libra.li@technexion.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* AMD Chipset */ -#define AMD_RS690_INT15 0x4E08 - -typedef struct __rs690_int15_regs__ -{ - u8 fun00_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID - u8 fun05_tv_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard -}rs690_int15_regs; - -typedef struct __rs690_vbios_regs__ -{ - rs690_int15_regs int15_regs; -}rs690_vbios_regs; - -/* Initialization VBIOS function */ -extern void vgabios_init(rs690_vbios_regs *vbios_regs); diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig deleted file mode 100644 index ad80e853c3..0000000000 --- a/src/mainboard/technexion/tim8690/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -if BOARD_TECHNEXION_TIM8690 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SOCKET_S1G1 - select NORTHBRIDGE_AMD_AMDK8 - select SOUTHBRIDGE_AMD_RS690 - select SOUTHBRIDGE_AMD_SB600 - select SUPERIO_ITE_IT8712F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_512 - select QRANK_DIMM_SUPPORT - select SET_FIDVID - -config MAINBOARD_DIR - string - default technexion/tim8690 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "TIM-8690" - -config MAX_CPUS - int - default 2 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_TECHNEXION_TIM8690 diff --git a/src/mainboard/technexion/tim8690/Kconfig.name b/src/mainboard/technexion/tim8690/Kconfig.name deleted file mode 100644 index 6080e4e564..0000000000 --- a/src/mainboard/technexion/tim8690/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_TECHNEXION_TIM8690 - bool "TIM-8690" diff --git a/src/mainboard/technexion/tim8690/acpi/ide.asl b/src/mainboard/technexion/tim8690/acpi/ide.asl deleted file mode 100644 index d5badfcb6b..0000000000 --- a/src/mainboard/technexion/tim8690/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/technexion/tim8690/acpi/routing.asl b/src/mainboard/technexion/tim8690/acpi/routing.asl deleted file mode 100644 index bcb14e7e37..0000000000 --- a/src/mainboard/technexion/tim8690/acpi/routing.asl +++ /dev/null @@ -1,254 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS690 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0012FFFF, 1, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 2, INTC, 0 }, - Package(){0x0013FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS690 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0012FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0013FFFF, 0, 0, 16 }, - Package(){0x0013FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 2, 0, 18 }, - Package(){0x0013FFFF, 3, 0, 19 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS690 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS690 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/technexion/tim8690/acpi/sata.asl b/src/mainboard/technexion/tim8690/acpi/sata.asl deleted file mode 100644 index 474e5ed6d2..0000000000 --- a/src/mainboard/technexion/tim8690/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00120000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/technexion/tim8690/acpi/usb.asl b/src/mainboard/technexion/tim8690/acpi/usb.asl deleted file mode 100644 index 638690697c..0000000000 --- a/src/mainboard/technexion/tim8690/acpi/usb.asl +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/technexion/tim8690/acpi_tables.c b/src/mainboard/technexion/tim8690/acpi_tables.c deleted file mode 100644 index 75834b6c7f..0000000000 --- a/src/mainboard/technexion/tim8690/acpi_tables.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/amd/amdk8_sysconf.h> -#include "northbridge/amd/amdk8/acpi.h" -#include <arch/cpu.h> -#include <cpu/amd/powernow.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - get_bus_conf(); - - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB600 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/technexion/tim8690/board_info.txt b/src/mainboard/technexion/tim8690/board_info.txt deleted file mode 100644 index dbda07e41b..0000000000 --- a/src/mainboard/technexion/tim8690/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: half -Board URL: http://www.technexion.com/index.php/tim-8690 diff --git a/src/mainboard/technexion/tim8690/cmos.layout b/src/mainboard/technexion/tim8690/cmos.layout deleted file mode 100644 index 104d51f4c2..0000000000 --- a/src/mainboard/technexion/tim8690/cmos.layout +++ /dev/null @@ -1,69 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb deleted file mode 100644 index 8d1df8be10..0000000000 --- a/src/mainboard/technexion/tim8690/devicetree.cb +++ /dev/null @@ -1,115 +0,0 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_S1G1 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x3050 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl deleted file mode 100644 index ae82a2a300..0000000000 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ /dev/null @@ -1,1674 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/amd/sb600/sb600.h> - -/* DefinitionBlock Statement */ -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "TECHNE", /* OEMID */ - "COREBOOT", /* TABLE ID */ - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve) - { - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - - Method(CIRQ, 0x00, NotSerialized) - { - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00120000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { /* HPET */ - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* HPET is visible */ - } - Method(_CRS, 0) { - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE IT8712F Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the IT8712F MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* IT8712F magic number */ - } - /* Exit the IT8712F MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - - /* - * Keyboard PME is routed to SB600 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("IT8712F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c deleted file mode 100644 index f9768b20bd..0000000000 --- a/src/mainboard/technexion/tim8690/fadt.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - -#include <string.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <device/device.h> -#include "southbridge/amd/sb600/sb600.h" - -/*extern*/ u16 pm_base = 0x800; -/* pm_base should be set in sb ACPI */ -/* pm_base should be got from bar2 of rs690. Here I compact ACPI - * registers into 32 bytes limit. - * */ - -#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */ -#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */ -#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */ -#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */ - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - pm_base &= 0xFFFF; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - - /* Prepare the header */ - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - /* disable system management mode by setting to 0: */ - fadt->smi_cmd = 0; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; - - pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - - /* CpuControl is in \_PR.CP00, 6 bytes */ - pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); - pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); - - pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */ - - pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); - - pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 20-2B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ - pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alrm work */ - fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ - fadt->flags = 0x0001c1a5;/* 0x25; */ - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c deleted file mode 100644 index b1b7270802..0000000000 --- a/src/mainboard/technexion/tim8690/get_bus_conf.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <string.h> -#include <stdint.h> -#include <stdlib.h> -#include <cpu/amd/multicore.h> - -#include <cpu/amd/amdk8_sysconf.h> - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u8 bus_rs690[8]; -u8 bus_sb600[2]; -u32 apicid_sb600; - -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* -* HT Chain device num, actually it is unit id base of every ht device in chain, -* assume every chain only have 4 ht device at most -*/ -u32 hcdnx[] = { - 0x20202020, -}; - -u32 sbdn_rs690; -u32 sbdn_sb600; - - - -static u32 get_bus_conf_done = 0; - -void get_bus_conf(void) -{ - u32 apicid_base; - struct device *dev; - int i; - - if (get_bus_conf_done == 1) - return; /* do it only once */ - get_bus_conf_done = 1; - - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for (i = 0; i < sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } - - get_sblk_pci1234(); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - sbdn_rs690 = sysconf.sbdn; - sbdn_sb600 = 0; - - for (i = 0; i < 2; i++) { - bus_sb600[i] = 0; - } - for (i = 0; i < 8; i++) { - bus_rs690[i] = 0; - } - - bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb600[0] = bus_rs690[0]; - - /* sb600 */ - dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4)); - if (dev) { - bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - - /* rs690 */ - for (i = 1; i < 8; i++) { - dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0)); - if (dev) { - bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } - - /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb600 = apicid_base + 0; -} diff --git a/src/mainboard/technexion/tim8690/irq_tables.c b/src/mainboard/technexion/tim8690/irq_tables.c deleted file mode 100644 index 4c2a48dff7..0000000000 --- a/src/mainboard/technexion/tim8690/irq_tables.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -#include <cpu/amd/amdk8_sysconf.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -extern u8 bus_rs690[8]; -extern u8 bus_sb600[2]; -extern unsigned long sbdn_sb600; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = bus_sb600[0]; - pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4; - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4, - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c deleted file mode 100644 index 2f2b453994..0000000000 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <device/pci_def.h> -#include <southbridge/amd/sb600/sb600.h> - -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ -#define SMBUS_IO_BASE 0x1000 - -extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) - - - - -/*************************************************** -* This board, the TIM-8690 has two Marvel 88e5056 PCI-E -* 10/100/1000 chips on board. -* Both of their pin PERSTn pins are connected to GPIO 5 of the -* SB600 southbridge. -****************************************************/ -static void enable_onboard_nic(void) -{ - - u8 byte; - struct device *sm_dev; - - printk(BIOS_INFO, "enable_onboard_nic.\n"); - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0x9a); - byte |= ( 1 << 7); - pci_write_config8(sm_dev, 0x9a, byte); - - byte = pm_ioread(0x59); - byte &= ~( 1<< 5); - pm_iowrite(0x59,byte); - - byte = pci_read_config8(sm_dev, 0xA8); - - byte |= (1 << 1); //set bit 1 to high - pci_write_config8(sm_dev, 0xA8, byte); -} - -/* set thermal config - */ -static void set_thermal_config(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); - - /* sb600 settings for thermal config */ - /* set SB600 GPIO 64 to GPIO with pull-up */ - byte = pm2_ioread(0x42); - byte &= 0x3f; - pm2_iowrite(0x42, byte); - - /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x56); - word |= 1 << 7; - pci_write_config16(sm_dev, 0x56, word); - - /* set GPIO 64 internal pull-up */ - byte = pm2_ioread(0xf0); - byte &= 0xee; - pm2_iowrite(0xf0, byte); - - /* set Talert to be active low */ - byte = pm_ioread(0x67); - byte &= ~(1 << 5); - pm_iowrite(0x67, byte); - - /* set Talert to generate ACPI event */ - byte = pm_ioread(0x3c); - byte &= 0xf3; - pm_iowrite(0x3c, byte); - - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ -} - -/************************************************* -* enable the dedicated function in tim8690 board. -* This function called early than rs690_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); - - enable_onboard_nic(); - set_thermal_config(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c deleted file mode 100644 index 9515931627..0000000000 --- a/src/mainboard/technexion/tim8690/mptable.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> -#include <arch/io.h> -#include <string.h> -#include <stdint.h> -#include <cpu/amd/amdk8_sysconf.h> - -extern u8 bus_rs690[8]; -extern u8 bus_sb600[2]; - -extern u32 apicid_sb600; - -extern u32 sbdn_rs690; -extern u32 sbdn_sb600; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - get_bus_conf(); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(bus_sb600[0], - PCI_DEVFN(sbdn_sb600 + 0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb600, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/technexion/tim8690/resourcemap.c b/src/mainboard/technexion/tim8690/resourcemap.c deleted file mode 100644 index 20a8d91bee..0000000000 --- a/src/mainboard/technexion/tim8690/resourcemap.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void setup_tim8690_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c deleted file mode 100644 index 67d0b06470..0000000000 --- a/src/mainboard/technexion/tim8690/romstage.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <cpu/amd/model_fxx_rev.h> -#include <northbridge/amd/amdk8/raminit.h> -#include <delay.h> -#include <spd.h> -#include <cpu/x86/lapic.h> - -#include <superio/ite/common/ite.h> -#include <superio/ite/it8712f/it8712f.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs690/early_setup.c" -#include "southbridge/amd/sb600/early_setup.c" -#include <northbridge/amd/amdk8/f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) - -void memreset(int controllers, const struct mem_controller *ctrl) { } -void activate_spd_rom(const struct mem_controller *ctrl) { } - -int spd_read_byte(u32 device, u32 address) -{ - return smbus_read_byte(device, address); -} - -#include <northbridge/amd/amdk8/amdk8.h> -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "lib/generic_sdram.c" -#include "resourcemap.c" -#include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/model_fxx/init_cpus.c" -#include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; - int needs_reset = 0; - u32 bsp_apicid = 0; - msr_t msr; - struct cpuid_result cpuid1; - struct sys_info *sysinfo = &sysinfo_car; - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - } - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - enable_rs690_dev8(); - sb600_lpc_init(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - ite_kill_watchdog(GPIO_DEV); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); - - setup_tim8690_resource_map(); - - setup_coherent_ht_domain(); - -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); - start_other_cores(); -#endif - wait_all_aps_started(bsp_apicid); - - ht_setup_chains_x(sysinfo); - - /* run _early_setup before soft-reset. */ - rs690_early_setup(); - sb600_early_setup(); - - /* Check to see if processor is capable of changing FIDVID */ - /* otherwise it will throw a GP# when reading FIDVID_STATUS */ - cpuid1 = cpuid(0x80000007); - if ((cpuid1.edx & 0x6) == 0x6 ) { - /* Read FIDVID_STATUS */ - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - - /* show final fid and vid */ - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - } else { - printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); - } - - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - rs690_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); - - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } - - allow_all_aps_stop(bsp_apicid); - - /* It's the time to set ctrl now; */ - printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", - sysinfo->nodes, sysinfo->ctrl, spd_addr); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - - rs690_before_pci_init(); - sb600_before_pci_init(); -} |