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authorLibra Li <libra.li@technexion.com>2009-10-13 16:56:58 +0000
committerMyles Watson <mylesgw@gmail.com>2009-10-13 16:56:58 +0000
commit7d3649a605cf5d535039f1932224cdeafc49f73b (patch)
tree3d9fb481c22d70f1157faf7cf79a01f7d874e3a2 /src/mainboard/technexion/tim8690
parentc270e896f0bf9c780f2c49fa258b1c225e61ec9d (diff)
This patch support for the Technexion Tim-5690 mainboard.
It's an embedded AMD RS690/SB600 mainboard. http://www.technexion.com/index.php/tim-5690 Myles added Kconfig support. Signed-off-by: Libra Li <libra.li@technexion.com> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/technexion/tim8690')
-rw-r--r--src/mainboard/technexion/tim8690/mainboard.c31
1 files changed, 14 insertions, 17 deletions
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index 30a4bc8a97..c607167bcb 100644
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -49,7 +49,7 @@ uint64_t uma_memory_base, uma_memory_size;
/***************************************************
-* This board, the TIM-8690 has two Marvel 88e5056 PCI-E
+* This board, the TIM-8690 has two Marvel 88e5056 PCI-E
* 10/100/1000 chips on board.
* Both of their pin PERSTn pins are connected to GPIO 5 of the
* SB600 southbridge.
@@ -57,28 +57,25 @@ uint64_t uma_memory_base, uma_memory_size;
static void enable_onboard_nic()
{
- u8 byte;
- device_t sm_dev;
-
-
- printk_info("enable_onboard_nic.\n");
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ u8 byte;
+ device_t sm_dev;
- byte = pci_read_config8(sm_dev, 0x9a);
- byte |= ( 1 << 7);
- pci_write_config8(sm_dev, 0x9a, byte);
+ printk_info("enable_onboard_nic.\n");
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- byte=pm_ioread(0x59);
- byte &= ~( 1<< 5);
- pm_iowrite(0x59,byte);
+ byte = pci_read_config8(sm_dev, 0x9a);
+ byte |= ( 1 << 7);
+ pci_write_config8(sm_dev, 0x9a, byte);
+ byte=pm_ioread(0x59);
+ byte &= ~( 1<< 5);
+ pm_iowrite(0x59,byte);
- byte = pci_read_config8(sm_dev, 0xA8);
+ byte = pci_read_config8(sm_dev, 0xA8);
- byte |= (1 << 1); //set bit 1 to high
- pci_write_config8(sm_dev, 0xA8, byte);
+ byte |= (1 << 1); //set bit 1 to high
+ pci_write_config8(sm_dev, 0xA8, byte);
}
/* set thermal config