diff options
| author | Jeremy Soller <jeremy@system76.com> | 2021-10-27 15:45:41 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-02 20:48:29 +0000 |
| commit | fdaccd875da610954e3bc1136fad8a3c70ceae71 (patch) | |
| tree | e6444aaeb61e51d84c6d52b979fddffb1e82f93f /src/mainboard/system76 | |
| parent | f74e42a542ab5a678b40a0e32d03f6a2449e45c9 (diff) | |
mb/system76/bonw14: Add System76 Bonobo Workstation 14
Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/system76')
19 files changed, 904 insertions, 0 deletions
diff --git a/src/mainboard/system76/bonw14/Kconfig b/src/mainboard/system76/bonw14/Kconfig new file mode 100644 index 0000000000..6f93e09de1 --- /dev/null +++ b/src/mainboard/system76/bonw14/Kconfig @@ -0,0 +1,56 @@ +if BOARD_SYSTEM76_BONW14 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_BAT_THRESHOLDS + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_HOTPLUG + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COMETLAKE_S + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_RDRESP_NEED_DELAY + +config MAINBOARD_DIR + default "system76/bonw14" + +config MAINBOARD_PART_NUMBER + default "bonw14" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Bonobo WS" + +config MAINBOARD_VERSION + default "bonw14" + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config UART_FOR_CONSOLE + default 2 + +config MAX_CPUS + default 20 + +config DIMM_MAX + default 4 + +config POST_DEVICE + default n + +endif diff --git a/src/mainboard/system76/bonw14/Kconfig.name b/src/mainboard/system76/bonw14/Kconfig.name new file mode 100644 index 0000000000..982a9cbfe5 --- /dev/null +++ b/src/mainboard/system76/bonw14/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SYSTEM76_BONW14 + bool "bonw14" diff --git a/src/mainboard/system76/bonw14/Makefile.inc b/src/mainboard/system76/bonw14/Makefile.inc new file mode 100644 index 0000000000..a866021880 --- /dev/null +++ b/src/mainboard/system76/bonw14/Makefile.inc @@ -0,0 +1,10 @@ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/system76/bonw14/acpi/dgpu.asl b/src/mainboard/system76/bonw14/acpi/dgpu.asl new file mode 100644 index 0000000000..6521ee947e --- /dev/null +++ b/src/mainboard/system76/bonw14/acpi/dgpu.asl @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (\_SB.PCI0.PEG0) +{ + Name (_ADR, 0x00010000) + + Device (PEGP) + { + Name (_ADR, 0) + + // Convert a byte to a hex string, trimming extra parts + Method (BHEX, 1) + { + Local0 = ToHexString(Arg0) + Return (Mid(Local0, SizeOf(Local0) - 2, 2)) + } + + // UUID to string + Method (IDST, 1) + { + Local0 = "" + Fprintf( + Local0, + "%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o", + BHEX(DerefOf(Arg0[3])), + BHEX(DerefOf(Arg0[2])), + BHEX(DerefOf(Arg0[1])), + BHEX(DerefOf(Arg0[0])), + BHEX(DerefOf(Arg0[5])), + BHEX(DerefOf(Arg0[4])), + BHEX(DerefOf(Arg0[7])), + BHEX(DerefOf(Arg0[6])), + BHEX(DerefOf(Arg0[8])), + BHEX(DerefOf(Arg0[9])), + BHEX(DerefOf(Arg0[10])), + BHEX(DerefOf(Arg0[11])), + BHEX(DerefOf(Arg0[12])), + BHEX(DerefOf(Arg0[13])), + BHEX(DerefOf(Arg0[14])), + BHEX(DerefOf(Arg0[15])) + ) + Return (Local0) + } + + // Safe hex conversion, checks type first + Method (SFST, 1) + { + Local0 = ObjectType(Arg0) + If (Local0 == 1 || Local0 == 2 || Local0 == 3) { + Return (ToHexString(Arg0)) + } Else { + Return (Concatenate("Type: ", Arg0)) + } + } + + Method (_DSM, 4, Serialized) + { + Debug = "NVIDIA _DSM" + Printf(" Arg0: %o", IDST(Arg0)) + Printf(" Arg1: %o", SFST(Arg1)) + Printf(" Arg2: %o", SFST(Arg2)) + Printf(" Arg3: %o", SFST(Arg3)) + + If (Arg0 == ToUUID ("d4a50b75-65c7-46f7-bfb7-41514cea0244")) { + If (Arg1 != 0x0102) { + Printf(" Invalid Arg1, return 0x80000002") + Return (0x80000002) + } + + If (Arg2 == 0) { + Printf(" Arg2 == 0x00, return supported functions") + Return (Buffer (4) { 0x01, 0x00, 0x10, 0x00 }) + } + + If (Arg2 == 0x14) { + Printf(" Arg2 == 0x14, return backlight package") + Return (Package (9) { + 0x8000A450, + 0x0200, + 0, + 0, + 1, + 1, + 200, + 32, + 1000 + }) + } + + Printf(" Unknown Arg2, return 0x80000002") + Return (0x80000002) + } + + Printf(" Unknown Arg0, return 0x80000001") + Return (0x80000001) + } + + // _DOD: Display Output Devices + Method (_DOD, 0, NotSerialized) + { + Return (Package (3) { + 0x80008320, + 0x80006330, + 0x8000A450 + }) + } + + Device (HDM0) + { + Name (_ADR, 0x80008320) + } + + Device (DSP0) + { + Name (_ADR, 0x80006330) + } + + Device (DSP1) + { + Name (_ADR, 0x8000A450) + } + } +} diff --git a/src/mainboard/system76/bonw14/acpi/gpe.asl b/src/mainboard/system76/bonw14/acpi/gpe.asl new file mode 100644 index 0000000000..7ef9a989c0 --- /dev/null +++ b/src/mainboard/system76/bonw14/acpi/gpe.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// GPP_K6 SCI +Method (_L06, 0, Serialized) { + Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == 1) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/system76/bonw14/acpi/mainboard.asl b/src/mainboard/system76/bonw14/acpi/mainboard.asl new file mode 100644 index 0000000000..0a4c64cc67 --- /dev/null +++ b/src/mainboard/system76/bonw14/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x03 /* GPP_K3 */ +#define EC_GPE_SWI 0x06 /* GPP_K6 */ +#include <ec/system76/ec/acpi/ec.asl> + +Scope (\_SB) { + #include "sleep.asl" +} + +Scope (\_GPE) { + #include "gpe.asl" +} + +#include "dgpu.asl" diff --git a/src/mainboard/system76/bonw14/acpi/sleep.asl b/src/mainboard/system76/bonw14/acpi/sleep.asl new file mode 100644 index 0000000000..48c50e075e --- /dev/null +++ b/src/mainboard/system76/bonw14/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/system76/bonw14/board_info.txt b/src/mainboard/system76/bonw14/board_info.txt new file mode 100644 index 0000000000..6a8b2da0b4 --- /dev/null +++ b/src/mainboard/system76/bonw14/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: bonw14 +Category: laptop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/bonw14/bootblock.c b/src/mainboard/system76/bonw14/bootblock.c new file mode 100644 index 0000000000..8d06adc9d7 --- /dev/null +++ b/src/mainboard/system76/bonw14/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/system76/bonw14/cmos.default b/src/mainboard/system76/bonw14/cmos.default new file mode 100644 index 0000000000..06b04332a2 --- /dev/null +++ b/src/mainboard/system76/bonw14/cmos.default @@ -0,0 +1,2 @@ +boot_option=Fallback +debug_level=Debug diff --git a/src/mainboard/system76/bonw14/cmos.layout b/src/mainboard/system76/bonw14/cmos.layout new file mode 100644 index 0000000000..ac817525dd --- /dev/null +++ b/src/mainboard/system76/bonw14/cmos.layout @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +984 16 h 0 check_sum + +enumerations + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 983 984 diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb new file mode 100644 index 0000000000..612711d91c --- /dev/null +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -0,0 +1,224 @@ +chip soc/intel/cannonlake + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 125, + .tdp_pl2_override = 160, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console + }" + + # Misc + register "AcousticNoiseMitigation" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "13" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "PMC_GPP_K" + register "gpe0_dw1" = "PMC_GPP_G" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + subsystemid 0x1558 0x7714 inherit + device pci 00.0 on end # Host Bridge + device pci 01.0 on # GPU Port + # PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU) + register "PcieClkSrcUsage[7]" = "0x40" + register "PcieClkSrcClkReq[7]" = "7" + + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end + # TODO: is this enough to disable iGPU? + device pci 02.0 off end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3 + end + device pci 14.2 on end # Shared SRAM + device pci 14.3 on # CNVi wifi + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataPortsEnable[1]" = "1" # SATA1A (SSD) + register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3) + register "SataPortsEnable[4]" = "1" # SATA4 (SSD2) + end + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1b.0 on # PCI Express Port 17 + # PCI Express root port #17 x4, Clock 14 (SSD2) + register "PcieRpEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "1" + register "PcieClkSrcUsage[14]" = "16" + register "PcieClkSrcClkReq[14]" = "14" + end + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 on # PCI Express Port 21 + # PCI Express root port #21 x4, Clock 15 (SSD3) + register "PcieRpEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "1" + register "PcieClkSrcUsage[15]" = "20" + register "PcieClkSrcClkReq[15]" = "15" + end + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1c.0 on # PCI Express Port 1 + # PCI Express root port #1 x4, Clock 6 (Thunderbolt) + register "PcieRpEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED + register "PcieClkSrcClkReq[6]" = "6" + end + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + # PCI Express root port #5 x4, Clock 10 (USB 3.2) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[10]" = "4" + register "PcieClkSrcClkReq[10]" = "10" + end + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 + # PCI Express root port #9 x4, Clock 8 (SSD) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[8]" = "8" + register "PcieClkSrcClkReq[8]" = "8" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 + # PCI Express root port #13 x1, Clock 0 (WLAN) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[0]" = "12" + register "PcieClkSrcClkReq[0]" = "0" + end + device pci 1d.5 on # PCI Express Port 14 + # PCI Express root port #14 x1, Clock 1 (GLAN) + register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" + register "PcieClkSrcUsage[1]" = "13" + register "PcieClkSrcClkReq[1]" = "1" + end + device pci 1d.6 on # PCI Express Port 15 + # PCI Express root port #15 x1, Clock 4 (Card Reader) + register "PcieRpEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "1" + register "PcieClkSrcUsage[4]" = "14" + register "PcieClkSrcClkReq[4]" = "4" + end + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0e01" + register "gen3_dec" = "0x00fc0f01" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/system76/bonw14/dsdt.asl b/src/mainboard/system76/bonw14/dsdt.asl new file mode 100644 index 0000000000..a48382b578 --- /dev/null +++ b/src/mainboard/system76/bonw14/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/bonw14/gpio.c b/src/mainboard/system76/bonw14/gpio.c new file mode 100644 index 0000000000..a80aa1475b --- /dev/null +++ b/src/mainboard/system76/bonw14/gpio.c @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // BATLOW_N + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT + PAD_CFG_GPI(GPD2, NATIVE, PWROK), // PCH_LAN_WAKE# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH + PAD_NC(GPD6, UP_20K), + PAD_CFG_GPI(GPD7, UP_20K, PWROK), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_CFG_GPI(GPD11, UP_20K, PWROK), // LANPHYPC + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0 + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1 + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2 + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // 10k pull up + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC + PAD_NC(GPP_A10, UP_20K), + _PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), // INTP_OUT + PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), // 10k pull up + PAD_CFG_GPI(GPP_A13, UP_20K, DEEP), // SUS_PWR_ACK + PAD_NC(GPP_A14, UP_20K), + PAD_CFG_GPI(GPP_A15, UP_20K, DEEP), // SUSACK# + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, UP_20K), + PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_A19, UP_20K, DEEP), // XFI_GAIN + PAD_CFG_GPO(GPP_A20, 1, DEEP), // GPP_A20 (MB det) + PAD_NC(GPP_A21, UP_20K), + PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), // GPP_A22 (MB det) + PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPP_A23 (MB det) + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_B1, UP_20K), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // BT_UART_WAKE_N + PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN + PAD_NC(GPP_B4, UP_20K), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GLAN_CLKREQ# + PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST), // GPIO_CR_RESET_R + PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), // CR_GPIO_WAKE_N_R + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // CR_CLKREQ# + PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST), // PRSNT# + PAD_CFG_GPO(GPP_B11, 1, DEEP), // PCIE_GLAN_RESET + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR + PAD_NC(GPP_B15, UP_20K), + PAD_NC(GPP_B16, UP_20K), + PAD_CFG_GPI(GPP_B17, UP_20K, DEEP), // LPSS_GSPI0_MISO + PAD_CFG_GPI(GPP_B18, UP_20K, DEEP), // LPSS_GSPI0_MOSI + PAD_NC(GPP_B19, UP_20K), + _PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000), // SMI#_3242 + PAD_NC(GPP_B21, UP_20K), + PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // EXI BOOT STALL STRAP + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // TLS CONFIDENTIALITY STRAP + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SMLINK0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SMLINK0_DATA + PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // ESPI/LPC SELECT STRAP + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SMC_CPU_THERM_R + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SMD_CPU_THERM + PAD_CFG_GPI(GPP_C8, NONE, PLTRST), // TPM_DET# + PAD_CFG_GPI(GPP_C9, NONE, DEEP), // GSYNC_ID + PAD_NC(GPP_C10, DN_20K), + PAD_CFG_GPO(GPP_C11, 1, DEEP), // FW_RST# + PAD_NC(GPP_C12, UP_20K), + PAD_NC(GPP_C13, UP_20K), + PAD_NC(GPP_C14, UP_20K), + PAD_NC(GPP_C15, UP_20K), + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // T_SDA + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // T_SCL + PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411 + PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411 + //PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), // UART2_RXD + //PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), // UART2_TXD + PAD_NC(GPP_C22, UP_20K), + PAD_NC(GPP_C23, UP_20K), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, UP_20K), + PAD_NC(GPP_D1, UP_20K), + PAD_NC(GPP_D2, UP_20K), + PAD_NC(GPP_D3, UP_20K), + PAD_NC(GPP_D4, UP_20K), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUR_CLKREQ0 + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), // M.2_BT_PCMIN + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), // M.2_BT_PCMCLK + PAD_NC(GPP_D9, UP_20K), + PAD_NC(GPP_D10, UP_20K), + PAD_NC(GPP_D11, UP_20K), + PAD_NC(GPP_D12, UP_20K), + PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), // 5825_I2C_DAT + PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), // 5825_I2C_CLK + PAD_NC(GPP_D15, UP_20K), + PAD_NC(GPP_D16, UP_20K), + PAD_NC(GPP_D17, UP_20K), + PAD_NC(GPP_D18, UP_20K), + PAD_NC(GPP_D19, UP_20K), + PAD_NC(GPP_D20, UP_20K), + PAD_NC(GPP_D21, UP_20K), + PAD_NC(GPP_D22, UP_20K), + PAD_NC(GPP_D23, UP_20K), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), // 10k pull up + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_DET_N + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), // VCCIO_0_CTRL + PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // SMI# + PAD_NC(GPP_E4, UP_20K), + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SSD1_SATA_DEVSLP + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // SSD3_SATA_DEVSLP + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED# + PAD_CFG_GPI(GPP_E9, UP_20K, DEEP), // RING OSCILLATOR BYPASS STRAP + PAD_CFG_GPI(GPP_E10, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP + PAD_CFG_GPI(GPP_E11, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP + PAD_CFG_GPI(GPP_E12, UP_20K, DEEP), // DFX TEST MODE + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2), // 10k pull up + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_DET_N + PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, RSMRST), // GPP_F2_TBT_RST# + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2), // 10k pull up + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2), // 10k pull up + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD4_SATA_DEVSLP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // SSD2_SATA_DEVSLP + PAD_NC(GPP_F7, UP_20K), + PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), // GPU_PWR_EN# + PAD_NC(GPP_F9, UP_20K), + PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // PCH_CONFIG_JUMPER + PAD_CFG_GPO(GPP_F11, 0, DEEP), // SSD1_PWR_DN# + PAD_CFG_GPI(GPP_F12, UP_20K, DEEP), + PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, UP_20K), + PAD_NC(GPP_F16, UP_20K), + PAD_NC(GPP_F17, UP_20K), + PAD_CFG_GPI(GPP_F18, UP_20K, DEEP), // GPIO_PCIESLOT_RST_R + PAD_NC(GPP_F19, UP_20K), + PAD_NC(GPP_F20, UP_20K), + PAD_NC(GPP_F21, UP_20K), + //PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F23, 0, DEEP), // GC_OFF_EN + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, UP_20K), + PAD_NC(GPP_G1, UP_20K), + PAD_NC(GPP_G2, UP_20K), + PAD_NC(GPP_G3, UP_20K), + PAD_NC(GPP_G4, UP_20K), + PAD_NC(GPP_G5, UP_20K), + PAD_NC(GPP_G6, UP_20K), + PAD_NC(GPP_G7, UP_20K), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // TBT_CLKREQ# + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // MXM_REQ# + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // SSD_CLKREQ# + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // PE_CLKREQ# + PAD_NC(GPP_H5, NONE), + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), // WLAN_GPIO_WAKE_N + PAD_CFG_GPO(GPP_H7, 0, DEEP), // PCIE_SSD2_RESET + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SSD2_CLKREQ# + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SSD3_CLKREQ# + PAD_NC(GPP_H10, NONE), + PAD_CFG_GPO(GPP_H11, 0, DEEP), // SSD3_PWR_DN# + PAD_CFG_GPI(GPP_H12, UP_20K, DEEP), // GPP_H_12 + PAD_NC(GPP_H13, UP_20K), + PAD_NC(GPP_H14, UP_20K), + _PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000), // GPP_H15_TBT_WAKE# + PAD_NC(GPP_H16, UP_20K), + PAD_NC(GPP_H17, UP_20K), + PAD_NC(GPP_H18, UP_20K), + PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), // GPIO_CARD_AUX + PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), // GPIO_CARD + PAD_NC(GPP_H21, UP_20K), + PAD_NC(GPP_H22, UP_20K), + PAD_NC(GPP_H23, UP_20K), + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), // GPPDPA_I0 + _PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), // GPPDPB_I1 + _PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), // DP_F_HPD + PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // 100k pull down + PAD_CFG_GPO(GPP_I5, 0, DEEP), // GPIO_TBT_RESET + PAD_CFG_GPI(GPP_I6, UP_20K, DEEP), // MXM_GPIO0 + PAD_CFG_GPI(GPP_I7, UP_20K, DEEP), // 10k pull up + PAD_CFG_GPI(GPP_I8, UP_20K, DEEP), // GPIO_WIFI_RESET_R + PAD_CFG_GPO(GPP_I9, 1, DEEP), // WLAN_EN + PAD_CFG_GPO(GPP_I10, 0, DEEP), // SSD2_PWR_DN# + PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // H_SKTOCC_N + PAD_CFG_GPO(GPP_I12, 0, DEEP), // PCIE_SSD3_RESET + PAD_CFG_GPO(GPP_I13, 0, DEEP), // PCIE_SSD1_RESET + PAD_NC(GPP_I14, UP_20K), + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // CPI_C10_GATE_N (VCCIO_3P3_PWRGATE) + PAD_NC(GPP_J2, UP_20K), + PAD_NC(GPP_J3, UP_20K), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT_R + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT_R + PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // EDP_OD_EN + PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), + + /* ------- GPIO Group GPP_K ------- */ + PAD_CFG_GPI(GPP_K0, UP_20K, DEEP), // PCH_GPIO_PK_MUTE + PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // PCH_GPIO_WOOFER_MUTE + PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // DGPU_PWRGD + _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI# + PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // GPU_EVENT#_R + PAD_CFG_GPO(GPP_K5, 0, DEEP), // DP_MUX_SW + _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI# + PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // E3100_PWR_EN + PAD_CFG_GPO(GPP_K8, 0, DEEP), // SSD4_PWR_DN# + PAD_CFG_GPI(GPP_K9, UP_20K, DEEP), // TBTA_HRESET + PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // MIC_SENSE_PCH + PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // XFI_SENSE_PCH + _PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT# + PAD_NC(GPP_K13, UP_20K), + PAD_CFG_GPO(GPP_K14, 0, DEEP), // 7411_TEST_R + PAD_NC(GPP_K15, UP_20K), + PAD_CFG_TERM_GPO(GPP_K16, 1, UP_20K, DEEP), // TBT_FORCE_PWR_R + PAD_NC(GPP_K17, UP_20K), + PAD_CFG_GPO(GPP_K18, 1, DEEP), // PCH_MUTE# + PAD_NC(GPP_K19, UP_20K), + PAD_CFG_GPI(GPP_K20, UP_20K, DEEP), // TEST_SETUP_MENU + PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN + //PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN# + PAD_CFG_GPO(GPP_K23, 1, RSMRST), // TBT_RTD3_PWR_EN_R +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/bonw14/gpio_early.c b/src/mainboard/system76/bonw14/gpio_early.c new file mode 100644 index 0000000000..42bbe42467 --- /dev/null +++ b/src/mainboard/system76/bonw14/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), // UART2_TXD + PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH + PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN# +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/bonw14/hda_verb.c b/src/mainboard/system76/bonw14/hda_verb.c new file mode 100644 index 0000000000..00f5fdb8d9 --- /dev/null +++ b/src/mainboard/system76/bonw14/hda_verb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x15587714, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15587714), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x40000000), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x4094022d), + AZALIA_PIN_CFG(0, 0x1e, 0x04451120), +}; + +const u32 pc_beep_verbs[] = { + // Enable DMIC microphone on ALC1220 + 0x02050036, + 0x02042a6a, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/bonw14/include/mainboard/gpio.h b/src/mainboard/system76/bonw14/include/mainboard/gpio.h new file mode 100644 index 0000000000..c6393beebb --- /dev/null +++ b/src/mainboard/system76/bonw14/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/bonw14/ramstage.c b/src/mainboard/system76/bonw14/ramstage.c new file mode 100644 index 0000000000..43ee54f50a --- /dev/null +++ b/src/mainboard/system76/bonw14/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <mainboard/gpio.h> + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/system76/bonw14/romstage.c b/src/mainboard/system76/bonw14/romstage.c new file mode 100644 index 0000000000..8f1687e29f --- /dev/null +++ b/src/mainboard/system76/bonw14/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg memcfg = { + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa2}, + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa6}, + }, + .rcomp_resistor = { 121, 75, 100 }, + .rcomp_targets = { 50, 26, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + // Allow memory clocks higher than 2933 MHz + memupd->FspmConfig.SaOcSupport = 1; + + // Set primary display to PCIe graphics + memupd->FspmConfig.PrimaryDisplay = 1; + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} |