diff options
author | Tim Crawford <tcrawford@system76.com> | 2022-12-30 10:05:38 -0700 |
---|---|---|
committer | Martin L Roth <gaumless@gmail.com> | 2023-01-05 17:55:17 +0000 |
commit | 7c92712cf0fdfd85fa518cda57e19d1cd7097108 (patch) | |
tree | 0faf94fe1f786c953c4a9dd5cb7f982963d875b2 /src/mainboard/system76 | |
parent | 06545e0744e322b2148f4cb52eb976737754e65b (diff) |
mb/system76/tgl-u: Add FSP-S configs per variant
Configure CPU PCIe RP and IOM per variant.
Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard/system76')
-rw-r--r-- | src/mainboard/system76/tgl-u/Makefile.inc | 1 | ||||
-rw-r--r-- | src/mainboard/system76/tgl-u/ramstage.c | 6 | ||||
-rw-r--r-- | src/mainboard/system76/tgl-u/variants/darp7/ramstage.c | 15 | ||||
-rw-r--r-- | src/mainboard/system76/tgl-u/variants/galp5/ramstage.c | 15 | ||||
-rw-r--r-- | src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c | 15 |
5 files changed, 46 insertions, 6 deletions
diff --git a/src/mainboard/system76/tgl-u/Makefile.inc b/src/mainboard/system76/tgl-u/Makefile.inc index 845c39aa19..ca14835be7 100644 --- a/src/mainboard/system76/tgl-u/Makefile.inc +++ b/src/mainboard/system76/tgl-u/Makefile.inc @@ -12,5 +12,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c SPD_SOURCES = samsung-M471A1G44AB0-CWE diff --git a/src/mainboard/system76/tgl-u/ramstage.c b/src/mainboard/system76/tgl-u/ramstage.c index d4cb898146..a01391a685 100644 --- a/src/mainboard/system76/tgl-u/ramstage.c +++ b/src/mainboard/system76/tgl-u/ramstage.c @@ -9,12 +9,6 @@ smbios_wakeup_type smbios_system_wakeup_type(void) return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; } -void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ - // Disable AER to fix suspend failing with some SSDs. - params->CpuPcieRpAdvancedErrorReporting[0] = 0; -} - static void mainboard_init(void *chip_info) { mainboard_configure_gpios(); diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c new file mode 100644 index 0000000000..a60587d5d4 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Disable AER to fix suspend failing with some SSDs. + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[5] = 1; // J_TYPEC2 +} diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c new file mode 100644 index 0000000000..a60587d5d4 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Disable AER to fix suspend failing with some SSDs. + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[5] = 1; // J_TYPEC2 +} diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c new file mode 100644 index 0000000000..2064836977 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Disable AER to fix suspend failing with some SSDs. + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[2] = 1; // J_TYPEC1 +} |