mb/system76/adl-p: Add Oryx Pro 10 as a variant

oryp10 is nearly identical to the oryp9, with the differences being:

- Uses DDR5 RAM instead of DDR4 RAM
- Uses Realtek ALC1306 instead of TI TAS5825M
- Has an option for OLED display

Change-Id: I0cf46cb5d10098dd31f0dc3c620db0c7e20ffba4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>

9 files changed, 657 insertions, 4 deletions

diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig
index 00f19fb51f..83176d1ca9 100644
--- a/src/mainboard/system76/adl/Kconfig
+++ b/src/mainboard/system76/adl/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9
+if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -8,8 +8,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_INTEL_USB4_RETIMER
 	select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP9
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9
-	select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+	select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
 	select HAVE_OPTION_TABLE
@@ -34,6 +34,7 @@ config VARIANT_DIR
 	default "galp6" if BOARD_SYSTEM76_GALP6
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
+	default "oryp10" if BOARD_SYSTEM76_ORYP10
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -43,18 +44,20 @@ config MAINBOARD_PART_NUMBER
 	default "galp6" if BOARD_SYSTEM76_GALP6
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
+	default "oryp10" if BOARD_SYSTEM76_ORYP10
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "Darter Pro" if BOARD_SYSTEM76_DARP8
 	default "Galago Pro" if BOARD_SYSTEM76_GALP6
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
-	default "Oryx Pro" if BOARD_SYSTEM76_ORYP9
+	default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
 
 config MAINBOARD_VERSION
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "galp6" if BOARD_SYSTEM76_GALP6
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
+	default "oryp10" if BOARD_SYSTEM76_ORYP10
 
 config CBFS_SIZE
 	default 0xA00000
diff --git a/src/mainboard/system76/adl/Kconfig.name b/src/mainboard/system76/adl/Kconfig.name
index f36b752d22..ee7b6ff678 100644
--- a/src/mainboard/system76/adl/Kconfig.name
+++ b/src/mainboard/system76/adl/Kconfig.name
@@ -9,3 +9,6 @@ config BOARD_SYSTEM76_LEMP11
 
 config BOARD_SYSTEM76_ORYP9
 	bool "oryp9"
+
+config BOARD_SYSTEM76_ORYP10
+	bool "oryp10"
diff --git a/src/mainboard/system76/adl/variants/oryp10/board_info.txt b/src/mainboard/system76/adl/variants/oryp10/board_info.txt
new file mode 100644
index 0000000000..2a167f5e2c
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/oryp10/board_info.txt
@@ -0,0 +1,2 @@
+Board name: oryp10
+Release year: 2022
diff --git a/src/mainboard/system76/adl/variants/oryp10/data.vbt b/src/mainboard/system76/adl/variants/oryp10/data.vbt
new file mode 100644
index 0000000000..df8bd14c62
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/oryp10/data.vbt
diff --git a/src/mainboard/system76/adl/variants/oryp10/gpio.c b/src/mainboard/system76/adl/variants/oryp10/gpio.c
new file mode 100644
index 0000000000..5c56f80e16
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/oryp10/gpio.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWN_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000), // INTP_8851
+	PAD_CFG_GPI(GPP_A7, NONE, PLTRST), // GC6_FB_EN_PCH
+	PAD_CFG_GPO(GPP_A8, 0, DEEP), // GPIO_LANRTD3
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A11, NONE), // GPU_PROCHOT#
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	// GPP_A14 (DGPU_PWR_EN) configured in bootblock
+	_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // G_DP_HDPD_E
+	PAD_NC(GPP_A16, NONE), // USB_OC3#
+	PAD_NC(GPP_A17, NONE),
+	_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
+	PAD_NC(GPP_A19, NONE),
+	_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000), // DP_F_HPD
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP), // PCIE4_WAKE_N
+	PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPIO4_NVVDD_EN
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	// GPP_B2 (DGPU_RST#_CPU) configured in bootblock
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GPPB_I2C2_SDA (Pantone)
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GPPB_I2C2_SCL (Pantone)
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // I2C3_SDA (IT8851)
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // I2C3_SCL (IT8851)
+	// GPP_B9 missing
+	// GPP_B10 missing
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_NC(GPP_B14, NONE), // Top swap override
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
+	// GPP_B19 missing
+	// GPP_B20 missing
+	// GPP_B21 missing
+	// GPP_B22 missing
+	PAD_CFG_GPO(GPP_B23, 0, DEEP), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_GPO(GPP_C5, 0, DEEP), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
+	// GPP_C8 missing
+	// GPP_C9 missing
+	// GPP_C10 missing
+	// GPP_C11 missing
+	// GPP_C12 missing
+	// GPP_C13 missing
+	// GPP_C14 missing
+	// GPP_C15 missing
+	// GPP_C16 missing
+	// GPP_C17 missing
+	// GPP_C18 missing
+	// GPP_C19 missing
+	// GPP_C20 missing
+	// GPP_C21 missing
+	// GPP_C22 missing
+	// GPP_C23 missing
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_GPO(GPP_D4, 1, PLTRST), // GPIO_LAN_EN
+	// GPP_D5 (SSD0_CLKREQ#) configured by FSP
+	PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
+	// GPP_D7 (WLAN_CLKREQ#) configured by FSP
+	// GPP_D8 (GPU_PCIE_CLKREQ#) configured by FSP
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SATA_LED#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP), // BOARD_ID4
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5
+	// GPP_E18 (TBTA_LSX2_TXD) configured by FSP
+	// GPP_E19 (TBTA_LSX2_RXD) configured by FSP
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE), // Strap
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	// GPP_F5 (CNVI_CLKREQ) configured by FSP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	// GPP_F8 missing
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_GPO(GPP_F12, 0, DEEP), // OVRM
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID6
+	PAD_CFG_GPI(GPP_F16, NONE, DEEP), // BOARD_ID7
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
+	PAD_NC(GPP_F18, NONE),
+	// GPP_F19 (CARD_CLKREQ#) configured by FSP
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M.2_PLT_RST_CNTRL2#
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M.2_PLT_RST_CNTRL3#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP (Touchpad)
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP (Touchpad)
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (Retimer)
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (Retimer)
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	// GPP_H10 (UART0_RX) configured in bootblock
+	// GPP_H11 (UART0_TX) configured in bootblock
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	// GPP_H14 missing
+	PAD_NC(GPP_H15, NONE),
+	// GPP_H16 missing
+	PAD_NC(GPP_H17, NONE),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	// GPP_H19 (SSD1_CLKREQ#) configured by FSP
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	// GPP_H23 (GLAN_CLKREQ#) configured by FSP
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_CFG_GPO(GPP_R5, 1, DEEP), // PCH_MUTE#
+	PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPR_DMIC_CLK
+	PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPR_DMIC_DATA
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/adl/variants/oryp10/gpio_early.c b/src/mainboard/system76/adl/variants/oryp10/gpio_early.c
new file mode 100644
index 0000000000..382fe0fd29
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/oryp10/gpio_early.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/adl/variants/oryp10/hda_verb.c b/src/mainboard/system76/adl/variants/oryp10/hda_verb.c
new file mode 100644
index 0000000000..3e1ec90425
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/oryp10/hda_verb.c
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155867f5, /* Subsystem ID */
+	152, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155867f5),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+
+	// Enable DMIC microphone on ALC1220
+	0x02050036, 0x02042a6a, 0x02050008, 0x0204800b,
+
+	// ALC1306 smart amp
+	0x02050027, 0x02040010, 0x02050029, 0x02040000,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003f,
+	0x0205002b, 0x02041000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040004,
+	0x0205002b, 0x02040600, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x0204c0c0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204ffd0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040080, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003a,
+	0x0205002b, 0x02040dfe, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x0204005d, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02040442, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040005,
+	0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040006,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040008,
+	0x0205002b, 0x0204b000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204002e,
+	0x0205002b, 0x02040800, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x020400c3, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x0204d4a0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x020400cc, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x0204400a, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x020400c1, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02040320, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040039,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003b,
+	0x0205002b, 0x0204ffff, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fc20, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x0204005d, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02049142, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x020400c0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fca0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fce0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fcf0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040080, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fce0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fca0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fc20, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040062,
+	0x0205002b, 0x02048000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040063,
+	0x0205002b, 0x02045f5f, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040064,
+	0x0205002b, 0x02042000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040065,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040066,
+	0x0205002b, 0x02044004, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040067,
+	0x0205002b, 0x02040802, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040068,
+	0x0205002b, 0x0204890f, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040069,
+	0x0205002b, 0x0204e021, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040070,
+	0x0205002b, 0x02048012, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040071,
+	0x0205002b, 0x02043450, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040072,
+	0x0205002b, 0x02040123, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040073,
+	0x0205002b, 0x02044543, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040074,
+	0x0205002b, 0x02042100, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040075,
+	0x0205002b, 0x02044321, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040076,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040046,
+	0x0205002b, 0x0204c22e, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040050,
+	0x0205002b, 0x02048200, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040051,
+	0x0205002b, 0x02040707, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040052,
+	0x0205002b, 0x02044090, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040090, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x0204721f, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040012,
+	0x0205002b, 0x0204dfdf, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204009e,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040004,
+	0x0205002b, 0x02040500, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040060,
+	0x0205002b, 0x02042213, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003a,
+	0x0205002b, 0x02041dfe, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003f,
+	0x0205002b, 0x02043000, 0x0205002c, 0x0204b424,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb
new file mode 100644
index 0000000000..ddf5876f67
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb
@@ -0,0 +1,201 @@
+chip soc/intel/alderlake
+	# HACK: Limit PL4 to prevent power off on battery power.
+	register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 115,
+		.tdp_psyspl2 = 135,
+		.tdp_pl4 = 72,
+	}"
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+	device domain 0 on
+		subsystemid 0x1558 0x65f5 inherit
+
+		device ref pcie5_0 on
+			# CPU PCIe RP#2 x8, Clock 3 (DGPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref igpu on
+			register "ddi_portA_config" = "1"
+			register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
+		end
+		device ref pcie4_0 on
+			# CPU PCIe RP#1 x4, Clock 0 (SSD1)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref pcie4_1 on
+			# CPU PCIe RP#3 x4, Clock 4 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(3)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB2
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Per-KB
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC2 (Thunderbolt)
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB2
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Per-KB""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Fingerprint""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref sata off end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			# PCIe RP#6 x1, Clock 6 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to 3.3VS?
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "6" # CARD_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			# PCIe RP#8 x1, Clock 5 (GLAN)
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to VDD3?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "5" # GLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# TYPEC2
+						use usb2_port9 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/system76/adl/variants/oryp10/romstage.c b/src/mainboard/system76/adl/variants/oryp10/romstage.c
new file mode 100644
index 0000000000..48714e0c85
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/oryp10/romstage.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.rcomp = { .resistor = 100, },
+		.ect = true,
+		.LpDdrDqDqsReTraining = 1,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}