mb/system76/oryp5: Add System76 Oryx Pro 5

Tested with TianoCore payload (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics
- Internal microphone
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux and Windows

Not working:

- Discrete/Hybrid graphics
- Internal speakers

These two require new drivers to work correctly, which will be added and
enabled later.

Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

17 files changed, 736 insertions, 0 deletions

diff --git a/src/mainboard/system76/oryp5/Kconfig b/src/mainboard/system76/oryp5/Kconfig
new file mode 100644
index 0000000000..6dcdbbf43e
--- /dev/null
+++ b/src/mainboard/system76/oryp5/Kconfig
@@ -0,0 +1,71 @@
+if BOARD_SYSTEM76_ORYP5
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COFFEELAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+
+config MAINBOARD_DIR
+	string
+	default "system76/oryp5"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "oryp5"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Oryx Pro"
+
+config MAINBOARD_VERSION
+	string
+	default "oryp5"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 12
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config POST_DEVICE
+	bool
+	default n
+
+endif
diff --git a/src/mainboard/system76/oryp5/Kconfig.name b/src/mainboard/system76/oryp5/Kconfig.name
new file mode 100644
index 0000000000..37221de9eb
--- /dev/null
+++ b/src/mainboard/system76/oryp5/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_ORYP5
+	bool "oryp5"
diff --git a/src/mainboard/system76/oryp5/Makefile.inc b/src/mainboard/system76/oryp5/Makefile.inc
new file mode 100644
index 0000000000..83ef3a5ca8
--- /dev/null
+++ b/src/mainboard/system76/oryp5/Makefile.inc
@@ -0,0 +1,8 @@
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += gpio_early.c
+
+ramstage-y += ramstage.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/system76/oryp5/acpi/gpe.asl b/src/mainboard/system76/oryp5/acpi/gpe.asl
new file mode 100644
index 0000000000..81022642e4
--- /dev/null
+++ b/src/mainboard/system76/oryp5/acpi/gpe.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_B23 SCI
+Method (_L17, 0, Serialized)
+{
+	Debug = Concatenate("GPE _L17: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}
diff --git a/src/mainboard/system76/oryp5/acpi/mainboard.asl b/src/mainboard/system76/oryp5/acpi/mainboard.asl
new file mode 100644
index 0000000000..a319ae627c
--- /dev/null
+++ b/src/mainboard/system76/oryp5/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x17 /* GPP_B23 */
+#define EC_GPE_SWI 0x26 /* GPP_G6 */
+#define EC_COLOR_KEYBOARD 1
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB)
+{
+	#include "sleep.asl"
+}
+
+Scope (\_GPE)
+{
+	#include "gpe.asl"
+}
diff --git a/src/mainboard/system76/oryp5/acpi/sleep.asl b/src/mainboard/system76/oryp5/acpi/sleep.asl
new file mode 100644
index 0000000000..f2b194c422
--- /dev/null
+++ b/src/mainboard/system76/oryp5/acpi/sleep.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1)
+{
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1)
+{
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
diff --git a/src/mainboard/system76/oryp5/board_info.txt b/src/mainboard/system76/oryp5/board_info.txt
new file mode 100644
index 0000000000..91e8d032d6
--- /dev/null
+++ b/src/mainboard/system76/oryp5/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: oryp5
+Category: laptop
+Release year: 2019
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/system76/oryp5/bootblock.c b/src/mainboard/system76/oryp5/bootblock.c
new file mode 100644
index 0000000000..ae416b4e77
--- /dev/null
+++ b/src/mainboard/system76/oryp5/bootblock.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}
diff --git a/src/mainboard/system76/oryp5/data.vbt b/src/mainboard/system76/oryp5/data.vbt
new file mode 100644
index 0000000000..e41aba6d11
--- /dev/null
+++ b/src/mainboard/system76/oryp5/data.vbt
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
new file mode 100644
index 0000000000..6cf5c94ea8
--- /dev/null
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -0,0 +1,203 @@
+chip soc/intel/cannonlake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 78,
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# Misc
+	register "AcousticNoiseMitigation" = "1"
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	register "tcc_offset" = "13"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "PMC_GPP_B"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x95e6 inherit
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on      # GPU Port
+			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
+			register "PcieClkSrcUsage[8]" = "0x40"
+			register "PcieClkSrcClkReq[8]" = "8"
+		end
+		device pci 02.0 on      # Integrated Graphics Device
+			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+		end
+		device pci 04.0 on      # SA Thermal device
+			register "Device4Enable" = "1"
+		end
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on      # USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
+			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C/DP
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # WLAN/Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C/DP
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
+			register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
+		end
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		device pci 14.3 on      # CNVi wifi
+			#chip drivers/intel/wifi
+			#	register "wake" = "PME_B0_EN_BIT"
+			#end
+		end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on      # I2C #0
+			# I2C HID not supported on PNP0f13
+		end
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on      # SATA
+			register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
+			register "SataPortsEnable[4]" = "1" # HDD (SATA4)
+		end
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 off end # PCI Express Port 17
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on      # PCI Express Port 21
+			# PCI Express root port #21 x4, Clock 11 (SSD2)
+			register "PcieRpEnable[20]" = "1"
+			register "PcieRpLtrEnable[20]" = "1"
+			register "PcieClkSrcUsage[11]" = "20"
+			register "PcieClkSrcClkReq[11]" = "11"
+		end
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on      # PCI Express Port 9
+			# PCI Express root port #9 x4, Clock 12 (SSD)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[12]" = "8"
+			register "PcieClkSrcClkReq[12]" = "12"
+		end
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 on      # PCI Express Port 14
+			# PCI Express root port #14 x1, Clock 13 (WLAN)
+			register "PcieRpEnable[13]" = "1"
+			register "PcieRpLtrEnable[13]" = "1"
+			register "PcieClkSrcUsage[13]" = "13"
+			register "PcieClkSrcClkReq[13]" = "13"
+		end
+		device pci 1d.6 on      # PCI Express Port 15
+			# PCI Express root port #15 x1, Clock 14 (GLAN)
+			register "PcieRpEnable[14]" = "1"
+			register "PcieRpLtrEnable[14]" = "1"
+			register "PcieClkSrcUsage[14]" = "14"
+			register "PcieClkSrcClkReq[14]" = "14"
+		end
+		device pci 1d.7 on      # PCI Express Port 16
+			# PCI Express root port #16 x1, Clock 15 (Card Reader)
+			register "PcieRpEnable[15]" = "1"
+			register "PcieRpLtrEnable[15]" = "1"
+			register "PcieClkSrcUsage[15]" = "15"
+			register "PcieClkSrcClkReq[15]" = "15"
+		end
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			register "gen1_dec" = "0x000c0081"
+			register "gen2_dec" = "0x00040069"
+			register "gen3_dec" = "0x00fc0e01"
+			register "gen4_dec" = "0x00fc0f01"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on      # Intel HDA
+			subsystemid 0x1558 0x96e1
+			register "PchHdaAudioLinkHda" = "1"
+		end
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end
diff --git a/src/mainboard/system76/oryp5/dsdt.asl b/src/mainboard/system76/oryp5/dsdt.asl
new file mode 100644
index 0000000000..3261c5994b
--- /dev/null
+++ b/src/mainboard/system76/oryp5/dsdt.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/system76/oryp5/gpio.c b/src/mainboard/system76/oryp5/gpio.c
new file mode 100644
index 0000000000..15e19617ba
--- /dev/null
+++ b/src/mainboard/system76/oryp5/gpio.c
@@ -0,0 +1,268 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_NC(GPD6, UP_20K),
+	PAD_CFG_GPI(GPD7, UP_20K, PWROK), /* GPD_7 (crystal input
+					     low = single ended,
+					     high = differential)
+					   */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // PCH_SUSCLK
+	PAD_NC(GPD9, UP_20K),
+	PAD_NC(GPD10, UP_20K),
+	PAD_CFG_TERM_GPO(GPD11, 1, NONE, DEEP), // LAN_DISABLE#
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // LPC_PIRQA#
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
+	PAD_NC(GPP_A10, UP_20K),
+	PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, PLTRST), // INTP_OUT
+	PAD_NC(GPP_A12, UP_20K),
+	PAD_NC(GPP_A13, UP_20K), // SUSWARN# (test point)
+	PAD_NC(GPP_A14, UP_20K), // (test point)
+	PAD_NC(GPP_A15, UP_20K), // SUS_PWR_ACK# (test point)
+	PAD_NC(GPP_A16, UP_20K),
+	PAD_NC(GPP_A17, UP_20K),
+	PAD_NC(GPP_A18, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_A20, NONE, DEEP), // PEX_WAKE#
+	PAD_NC(GPP_A21, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // WLAN_SSD2_GPIO1
+	PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP), // WLAN_SSD2_GPIO
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_GPI(GPP_B0, UP_20K, DEEP), // TPM_PIRQ#
+	PAD_NC(GPP_B1, UP_20K),
+	PAD_NC(GPP_B2, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_RF_KILL_R_N
+	PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // WIFI_RF_KILL_R_N
+	PAD_NC(GPP_B5, UP_20K),
+	PAD_NC(GPP_B6, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST), // CR_GPIO_RST#
+	PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST), // CR_GPIO_WAKE#
+	PAD_NC(GPP_B9, UP_20K),
+	PAD_NC(GPP_B10, UP_20K),
+	PAD_NC(GPP_B11, UP_20K),
+	PAD_CFG_GPI(GPP_B12, UP_20K, DEEP), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_NC(GPP_B15, UP_20K),
+	PAD_NC(GPP_B16, UP_20K),
+	PAD_NC(GPP_B17, UP_20K),
+	PAD_NC(GPP_B18, UP_20K), // LPSS_GSPI0_MOSI (test point)
+	PAD_NC(GPP_B19, UP_20K),
+	PAD_CFG_GPI_SMI(GPP_B20, NONE, DEEP, EDGE_SINGLE, NONE), // SMI#
+	PAD_NC(GPP_B21, UP_20K),
+	PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI
+	PAD_CFG_GPI_SCI_LOW(GPP_B23, UP_20K, PLTRST, LEVEL), // SCI#
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // GPP_C2_BT_UART_WAKE_N
+	PAD_NC(GPP_C3, UP_20K),
+	PAD_NC(GPP_C4, UP_20K),
+	PAD_CFG_GPI(GPP_C5, UP_20K, DEEP), // M.2_WLAN_WIFI_WAKE_N
+	PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), // SMC_CPU_THERM
+	PAD_CFG_GPI(GPP_C7, UP_20K, DEEP), // SMD_CPU_THERM
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
+	PAD_CFG_GPI(GPP_C9, DN_20K, DEEP), // BOARD_ID1
+	PAD_CFG_GPI(GPP_C10, DN_20K, DEEP), // BOARD_ID2
+	PAD_CFG_GPI(GPP_C11, DN_20K, DEEP), // BOARD_ID3
+	PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
+	PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, DEEP), // GPU_EVENT#
+	PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL1#
+	PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL2#
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411_I2C
+	PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411_I2C
+	//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_NF(GPP_C22, UP_20K, DEEP, NF1), // UART2_RTS# / LAN_PLT_RST#
+	PAD_CFG_NF(GPP_C23, UP_20K, DEEP, NF1), // BOARD_ID4
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, UP_20K),
+	PAD_NC(GPP_D1, UP_20K),
+	PAD_NC(GPP_D2, UP_20K),
+	PAD_NC(GPP_D3, UP_20K),
+	PAD_NC(GPP_D4, UP_20K),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUT_CLKREQ0
+	PAD_CFG_GPI(GPP_D7, UP_20K, DEEP), // M.2_BT_PCMIN
+	PAD_CFG_GPI(GPP_D8, UP_20K, DEEP), // M.2_BT_PCMCLK
+	PAD_NC(GPP_D9, UP_20K),
+	PAD_NC(GPP_D10, UP_20K),
+	PAD_NC(GPP_D11, UP_20K),
+	PAD_NC(GPP_D12, UP_20K),
+	PAD_NC(GPP_D13, NONE), // 10k pull up
+	PAD_NC(GPP_D14, NONE), // 10k pull up
+	PAD_NC(GPP_D15, UP_20K),
+	PAD_NC(GPP_D16, UP_20K),
+	PAD_NC(GPP_D17, UP_20K),
+	PAD_NC(GPP_D18, UP_20K),
+	PAD_NC(GPP_D19, UP_20K),
+	PAD_NC(GPP_D20, UP_20K),
+	PAD_NC(GPP_D21, UP_20K),
+	PAD_NC(GPP_D22, UP_20K),
+	PAD_NC(GPP_D23, UP_20K),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, UP_20K),
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_PEDET
+	PAD_NC(GPP_E2, UP_20K),
+	PAD_NC(GPP_E3, UP_20K),
+	PAD_NC(GPP_E4, UP_20K),
+	PAD_CFG_GPI(GPP_E5, UP_20K, DEEP), // M2_P0_SATA_DEVSLP
+	PAD_NC(GPP_E6, UP_20K),
+	PAD_CFG_GPI_APIC_EDGE_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN#
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
+	PAD_NC(GPP_E9, UP_20K), // USB_OC0# (test point)
+	PAD_NC(GPP_E10, UP_20K), // USB_OC1# (test point)
+	PAD_NC(GPP_E11, UP_20K), // USB_OC2# (test point)
+	PAD_NC(GPP_E12, UP_20K), // USB_OC3# (test point)
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, UP_20K),
+	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_PEDET
+	PAD_NC(GPP_F2, UP_20K),
+	PAD_NC(GPP_F3, UP_20K),
+	PAD_NC(GPP_F4, UP_20K),
+	PAD_NC(GPP_F5, UP_20K),
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // M2_P4_SATA_DEVSLP
+	PAD_NC(GPP_F7, UP_20K),
+	PAD_NC(GPP_F8, UP_20K),
+	PAD_NC(GPP_F9, UP_20K),
+	PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // BIOS_REC
+	PAD_CFG_GPI(GPP_F11, UP_20K, DEEP), // GPP_F11
+	PAD_NC(GPP_F12, UP_20K),
+	PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), // GP39_GFX_CRB_DETECT
+	PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // H_SKTOCC_N
+	PAD_NC(GPP_F15, UP_20K), // USB_OC4# (test point)
+	PAD_NC(GPP_F16, UP_20K),
+	PAD_NC(GPP_F17, UP_20K),
+	PAD_NC(GPP_F18, UP_20K), // USB_OC7# (test point)
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+	PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, UP_20K),
+	PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), // CNVI_WIGIG_DET#
+	PAD_NC(GPP_G2, UP_20K),
+	PAD_NC(GPP_G3, UP_20K),
+	PAD_NC(GPP_G4, UP_20K),
+	PAD_NC(GPP_G5, UP_20K),
+	PAD_CFG_GPI_SCI_LOW(GPP_G6, NONE, DEEP, LEVEL), // SWI#
+	PAD_NC(GPP_G7, UP_20K),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, UP_20K),
+	PAD_NC(GPP_H1, UP_20K),
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // CLK_REQ9_PEG#
+	PAD_NC(GPP_H3, UP_20K),
+	PAD_NC(GPP_H4, UP_20K),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // CLK_REQ12_SSD2#
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CLK_REQ13_SSD1#
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // GPP_H_0_SRCCLKREQB_14
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CLK_REQ15_LAN#
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CLK_REQ16_CARD#
+	PAD_NC(GPP_H10, UP_20K),
+	PAD_NC(GPP_H11, UP_20K),
+	PAD_NC(GPP_H12, UP_20K), // GPP_H_12 (test point)
+	PAD_NC(GPP_H13, UP_20K),
+	PAD_NC(GPP_H14, UP_20K),
+	PAD_NC(GPP_H15, NONE), // GPP_H15 (reserved)
+	PAD_NC(GPP_H16, UP_20K),
+	PAD_NC(GPP_H17, UP_20K),
+	PAD_NC(GPP_H18, UP_20K),
+	PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), // GPIO_CARD1
+	PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), // GPIO_CARD
+	PAD_CFG_GPI(GPP_H21, DN_20K, DEEP), // 4.7k pull up, 20k pull down
+	PAD_NC(GPP_H22, UP_20K),
+	PAD_NC(GPP_H23, UP_20K),
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_GPI_SCI_LOW(GPP_I0, NONE, DEEP, EDGE_BOTH), // G_DP_DHPD_A
+	PAD_CFG_GPI_SCI_LOW(GPP_I1, NONE, DEEP, EDGE_BOTH), // HDMI_HPD
+	PAD_CFG_GPI_SCI_LOW(GPP_I2, NONE, DEEP, EDGE_BOTH), // G_DP_DHPD_E
+	PAD_NC(GPP_I3, UP_20K),
+	PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HDP
+	PAD_NC(GPP_I5, UP_20K),
+	PAD_NC(GPP_I6, UP_20K),
+	PAD_NC(GPP_I7, UP_20K),
+	PAD_NC(GPP_I8, UP_20K),
+	PAD_NC(GPP_I9, UP_20K),
+	PAD_NC(GPP_I10, UP_20K),
+	PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // H_SKTOCC_N
+	PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN
+	PAD_NC(GPP_I13, UP_20K),
+	PAD_NC(GPP_I14, UP_20K),
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1
+	PAD_NC(GPP_J2, UP_20K),
+	PAD_NC(GPP_J3, UP_20K),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // M.2_CNV_VRI_DT_BT_UART0_RTS
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // M.2_CNV_BRI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // M.2_CNV_RGI_DT_BT_UART0_TX
+	PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // M.2_CNV_RGI_RSP
+	PAD_NC(GPP_J8, UP_20K),
+	PAD_CFG_GPI(GPP_J9, UP_20K, DEEP), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_J10, UP_20K),
+	PAD_NC(GPP_J11, UP_20K),
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_NC(GPP_K0, UP_20K),
+	PAD_NC(GPP_K1, UP_20K),
+	PAD_NC(GPP_K2, UP_20K),
+	PAD_NC(GPP_K3, UP_20K),
+	PAD_NC(GPP_K4, UP_20K),
+	PAD_NC(GPP_K5, UP_20K),
+	PAD_NC(GPP_K6, UP_20K),
+	PAD_NC(GPP_K7, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // SATA_M2_PWR_EN1
+	PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), // SATA_M2_PWR_EN2
+	PAD_NC(GPP_K10, UP_20K),
+	PAD_NC(GPP_K11, UP_20K),
+	PAD_NC(GPP_K12, UP_20K),
+	PAD_NC(GPP_K13, UP_20K),
+	// GPP_K_14_GSXDIN (test point), 7411_TEST_R
+	PAD_CFG_TERM_GPO(GPP_K14, 0, UP_20K, DEEP),
+	PAD_NC(GPP_K15, UP_20K),
+	PAD_NC(GPP_K16, UP_20K),
+	PAD_NC(GPP_K17, UP_20K),
+	PAD_NC(GPP_K18, UP_20K),
+	PAD_NC(GPP_K19, UP_20K),
+	PAD_NC(GPP_K20, UP_20K),
+	PAD_NC(GPP_K21, UP_20K),
+	PAD_NC(GPP_K22, UP_20K),
+	PAD_NC(GPP_K23, UP_20K),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/oryp5/gpio_early.c b/src/mainboard/system76/oryp5/gpio_early.c
new file mode 100644
index 0000000000..80f37c6553
--- /dev/null
+++ b/src/mainboard/system76/oryp5/gpio_early.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/oryp5/hda_verb.c b/src/mainboard/system76/oryp5/hda_verb.c
new file mode 100644
index 0000000000..a8e4abbad4
--- /dev/null
+++ b/src/mainboard/system76/oryp5/hda_verb.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155896e1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155896e1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140), // DMIC
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D)
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A)
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // CENTER/LFE (Port-G)
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // SIDE (Port-H)
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11050), // MIC1 (Port-B)
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // MIC2 (Port-F)
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // LINE1 (Port-C)
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110), // LINE2 (Port-E)
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), // PCBEEP
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451130), // S/PDIF-OUT
+};
+
+const u32 pc_beep_verbs[] = {
+	// Enable DMIC microphone on ALC1220
+	0x02050036,
+	0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/oryp5/include/mainboard/gpio.h b/src/mainboard/system76/oryp5/include/mainboard/gpio.h
new file mode 100644
index 0000000000..c6393beebb
--- /dev/null
+++ b/src/mainboard/system76/oryp5/include/mainboard/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/system76/oryp5/ramstage.c b/src/mainboard/system76/oryp5/ramstage.c
new file mode 100644
index 0000000000..43ee54f50a
--- /dev/null
+++ b/src/mainboard/system76/oryp5/ramstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <mainboard/gpio.h>
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};
diff --git a/src/mainboard/system76/oryp5/romstage.c b/src/mainboard/system76/oryp5/romstage.c
new file mode 100644
index 0000000000..455a2bb919
--- /dev/null
+++ b/src/mainboard/system76/oryp5/romstage.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.rcomp_resistor = { 121, 75, 100 },
+	.rcomp_targets = { 50, 25, 20, 20, 26 },
+	.dq_pins_interleaved = 1,
+	.vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	// Allow memory speeds higher than 2666 MT/s
+	memupd->FspmConfig.SaOcSupport = 1;
+
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}