mb/system76/tgl-u: Add FSP-S configs per variant

Configure CPU PCIe RP and IOM per variant.

Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>

5 files changed, 46 insertions, 6 deletions

diff --git a/src/mainboard/system76/tgl-u/Makefile.inc b/src/mainboard/system76/tgl-u/Makefile.inc
index 845c39aa19..ca14835be7 100644
--- a/src/mainboard/system76/tgl-u/Makefile.inc
+++ b/src/mainboard/system76/tgl-u/Makefile.inc
@@ -12,5 +12,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
 
 SPD_SOURCES = samsung-M471A1G44AB0-CWE
diff --git a/src/mainboard/system76/tgl-u/ramstage.c b/src/mainboard/system76/tgl-u/ramstage.c
index d4cb898146..a01391a685 100644
--- a/src/mainboard/system76/tgl-u/ramstage.c
+++ b/src/mainboard/system76/tgl-u/ramstage.c
@@ -9,12 +9,6 @@ smbios_wakeup_type smbios_system_wakeup_type(void)
 	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
 }
 
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	// Disable AER to fix suspend failing with some SSDs.
-	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
-}
-
 static void mainboard_init(void *chip_info)
 {
 	mainboard_configure_gpios();
diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
new file mode 100644
index 0000000000..a60587d5d4
--- /dev/null
+++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Disable AER to fix suspend failing with some SSDs.
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+}
diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
new file mode 100644
index 0000000000..a60587d5d4
--- /dev/null
+++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Disable AER to fix suspend failing with some SSDs.
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+}
diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
new file mode 100644
index 0000000000..2064836977
--- /dev/null
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Disable AER to fix suspend failing with some SSDs.
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[2] = 1; // J_TYPEC1
+}