diff options
author | Tim Crawford <tcrawford@system76.com> | 2023-05-16 12:41:31 -0600 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-22 12:46:38 +0000 |
commit | 930dbc0d0428e4e7726bd6f23acd3f5115dd85be (patch) | |
tree | 3bb682632314e751fc99d1963dbec5a718404158 /src/mainboard/system76/rpl/dsdt.asl | |
parent | 2049bb9b2c04738388ae97b6ed6e84e1be84ae21 (diff) |
mb/system76/rpl: Add Gazelle 18
The Gazelle 18 (gaze18) is a Raptor Lake-H board.
Tested with a custom TianoCore UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots
- M.2 NVMe SSD slot
- M.2 SATA SSD slot
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.6
Not working:
- Discrete/Hybrid graphics
Change-Id: I4599bf12c0f3048f9328f336cc8971400f5fd1a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard/system76/rpl/dsdt.asl')
-rw-r--r-- | src/mainboard/system76/rpl/dsdt.asl | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/system76/rpl/dsdt.asl b/src/mainboard/system76/rpl/dsdt.asl new file mode 100644 index 0000000000..df4681b4e6 --- /dev/null +++ b/src/mainboard/system76/rpl/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} |