diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-01-08 20:47:11 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:29:38 +0000 |
| commit | 45b6080561748fe579c8ee901811cf4043383c2f (patch) | |
| tree | b9f37ad3e3962571401fafa2578788f0feb27d5a /src/mainboard/system76/oryp8 | |
| parent | 9f0285b6fe46d6ec76faad0c099239c227e5caa1 (diff) | |
soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/system76/oryp8')
| -rw-r--r-- | src/mainboard/system76/oryp8/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index e6372fd8ab..b85818d892 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -188,6 +188,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 6 (SSD2) @@ -195,6 +196,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[6]" = "8" register "PcieClkSrcClkReq[6]" = "6" + register "PcieRpSlotImplemented[8]" = "1" end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel |