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authorMichael Niewöhner <foss@mniewoehner.de>2021-09-27 19:26:20 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2021-10-12 18:25:35 +0000
commitd2fadda52a5df72dbaedeed5c7f1c94bedbfd898 (patch)
tree83fd074be667a2a542e53636d4a8e165a9513a75 /src/mainboard/system76/lemp10
parent87e0b5b1d741179e4ce63c9950ad91f265417283 (diff)
soc/intel: replace dt option PmTimerDisabled by Kconfig
Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/system76/lemp10')
-rw-r--r--src/mainboard/system76/lemp10/Kconfig4
-rw-r--r--src/mainboard/system76/lemp10/devicetree.cb4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/system76/lemp10/Kconfig b/src/mainboard/system76/lemp10/Kconfig
index 637c90285d..1b6eec4a77 100644
--- a/src/mainboard/system76/lemp10/Kconfig
+++ b/src/mainboard/system76/lemp10/Kconfig
@@ -52,4 +52,8 @@ config POST_DEVICE
config UART_FOR_CONSOLE
default 2
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+ default n
+
endif
diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb
index f286ab50a0..1362b3d81a 100644
--- a/src/mainboard/system76/lemp10/devicetree.cb
+++ b/src/mainboard/system76/lemp10/devicetree.cb
@@ -26,10 +26,6 @@ chip soc/intel/tigerlake
.tdp_pl2_override = 30,
}"
-# Finalize (soc/intel/tigerlake/finalize.c)
- # PM Timer Disabled, saves power
- register "PmTimerDisabled" = "1"
-
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
# Enable C6 DRAM
register "enable_c6dram" = "1"