diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 20:32:15 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:44:13 +0000 |
| commit | 4b7220398923af42fa39a7fcb532daf797510f77 (patch) | |
| tree | f338082fc94ba81015f56348d48fe159fc238201 /src/mainboard/system76/kbl-u | |
| parent | df7de392ef5f8e1654df96a1a050820eb3779012 (diff) | |
skl mainboards/dt: Move serirq setting into LPC device scope
Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/system76/kbl-u')
| -rw-r--r-- | src/mainboard/system76/kbl-u/devicetree.cb | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 38578e06be..e4658a72e6 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -18,9 +18,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART }" - # Serial IRQ - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Power register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -172,6 +169,8 @@ chip soc/intel/skylake register "PcieRpLtrEnable[8]" = "1" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" register "gen3_dec" = "0x00040069" |