diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-10-26 15:42:16 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-10-30 14:00:48 +0000 |
| commit | ee1fd54aef8ec0aba9e3dc01111251e1ae6b9d12 (patch) | |
| tree | c80d54121beec1c097e124ed7f3891edb71333ad /src/mainboard/system76/kbl-u/devicetree.cb | |
| parent | d163253ba047515e3317e9da38aa7cc5714a7f0c (diff) | |
mb/system76/{tgl,skl}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/system76/kbl-u/devicetree.cb')
| -rw-r--r-- | src/mainboard/system76/kbl-u/devicetree.cb | 34 |
1 files changed, 19 insertions, 15 deletions
diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index bcd1130f91..3b84d7fdbf 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -110,26 +110,30 @@ chip soc/intel/skylake device ref igpu on end device ref sa_thermal on end device ref south_xhci on - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right - register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left - register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port right */ + [1] = USB2_PORT_FLEX(OC_SKIP), /* 3G / LTE */ + [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port right */ + [3] = USB2_PORT_FLEX(OC_SKIP), /* Camera */ + [4] = USB2_PORT_FLEX(OC_SKIP), /* Bluetooth */ + [6] = USB2_PORT_FLEX(OC_SKIP), /* Type-A port left */ + [7] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port right */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port right */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type C port right */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port left */ + }" end device ref thermal on end device ref sata on register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[2]" = "1" register "SataSpeedLimit" = "2" + register "SataPortsEnable" = "{ + [0] = 1, + [2] = 1, + }" end device ref pcie_rp1 on # Root port #1 x4 (TBT) |