summaryrefslogtreecommitdiff
path: root/src/mainboard/system76/galp5/devicetree.cb
diff options
context:
space:
mode:
authorTim Crawford <tcrawford@system76.com>2021-10-27 15:14:54 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-11-04 01:58:07 +0000
commitc3ced8fa4e3fc5ef9193d19549974f862dcb2455 (patch)
treebd11796341bc73dfe963bf32b052093d5c5ada8e /src/mainboard/system76/galp5/devicetree.cb
parenta6b3af927cb7005cf664e2065dbfcc49b0b295ca (diff)
mb/system76/*: Enable HECI device
The HECI device needs to be enabled to send the commands to have the CSME change between Soft Temporary Disable mode and Normal mode. Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard/system76/galp5/devicetree.cb')
-rw-r--r--src/mainboard/system76/galp5/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb
index cf3a75e50f..b0fa5243fb 100644
--- a/src/mainboard/system76/galp5/devicetree.cb
+++ b/src/mainboard/system76/galp5/devicetree.cb
@@ -256,7 +256,6 @@ chip soc/intel/tigerlake
register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
end
device ref heci1 on
- # TODO Disable ME and HECI
register "HeciEnabled" = "1"
end
device ref uart2 on