mb/system76/cml-u/dt: Make use of chipset devicetree

Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.

Change-Id: Ic33bf07041a8c966dce66109c577621513147609
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78838
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 31 insertions, 73 deletions

diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb
index 07c56b4b9f..7eaa0e7b57 100644
--- a/src/mainboard/system76/cml-u/devicetree.cb
+++ b/src/mainboard/system76/cml-u/devicetree.cb
@@ -59,59 +59,21 @@ chip soc/intel/cannonlake
 	device cpu_cluster 0 on end
 
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on      # Integrated Graphics Device
+		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device pci 04.0 on      # SA Thermal device
+		device ref dptf		on
 			register "Device4Enable" = "1"
 		end
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 13.0 off end # Integrated Sensor Hub
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.3 on      # CNVi wifi
+		device ref thermal	on	end
+		device ref cnvi_wifi	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end
 			end
 		end
-		device pci 14.5 off end # SDCard
-		device pci 15.1 off end # I2C #1
-		device pci 15.2 off end # I2C #2
-		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 19.0 off end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 off end # eMMC
-		device pci 1c.0 off end # PCI Express Port 1
-		device pci 1c.1 off end # PCI Express Port 2
-		device pci 1c.2 off end # PCI Express Port 3
-		device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 off end # PCI Express Port 5
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 off end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 off end # UART #0
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on      # LPC Interface
+		device ref uart2	on	end
+		device ref lpc_espi	on
 			register "gen1_dec" = "0x00040069"
 			register "gen2_dec" = "0x00fc0e01"
 			register "gen3_dec" = "0x00fc0f01"
@@ -119,13 +81,9 @@ chip soc/intel/cannonlake
 				device pnp 0c31.0 on end
 			end
 		end
-		device pci 1f.1 off end # P2SB
-		device pci 1f.2 hidden end # Power Management Controller
-		device pci 1f.3 on      # Intel HDA
+		device ref hda		on
 			register "PchHdaAudioLinkHda" = "1"
 		end
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
+		device ref smbus	on	end
 	end
 end
diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
index 17b1ba14f8..36744e9309 100644
--- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
@@ -4,7 +4,7 @@ chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1404 inherit
 
-		device pci 14.0 on      # USB xHCI
+		device ref xhci		on
 			register "usb2_ports" = "{
 				[0] = USB2_PORT_MID(OC_SKIP),		/* Type-A port 1 */
 				[1] = USB2_PORT_MID(OC_SKIP),		/* 3G / LTE */
@@ -22,7 +22,7 @@ chip soc/intel/cannonlake
 				[5] = USB3_PORT_EMPTY,			/* Used by TBT */
 			}"
 		end
-		device pci 15.0 on      # I2C #0
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA1202""
 				register "generic.desc" = ""Synaptics Touchpad""
@@ -32,13 +32,13 @@ chip soc/intel/cannonlake
 				device i2c 2c on end
 			end
 		end
-		device pci 17.0 on      # SATA
+		device ref sata		on
 			register "SataPortsEnable" = "{
 				[0] = 1,
 				[2] = 1,
 			}"
 		end
-		device pci 1c.4 on      # PCI Express Port 5
+		device ref pcie_rp5	on
 			# PCI Express Root port #5 x4, Clock 4 (TBT)
 			register "PcieRpEnable[4]" = "1"
 			register "PcieRpLtrEnable[4]" = "1"
@@ -46,28 +46,28 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[4]" = "4"
 			register "PcieClkSrcClkReq[4]" = "4"
 		end
-		device pci 1d.0 on      # PCI Express Port 9
+		device ref pcie_rp9	on
 			# PCI Express Root port #9 x1, Clock 3 (LAN)
 			register "PcieRpEnable[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "1"
 			register "PcieClkSrcUsage[3]" = "8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
-		device pci 1d.1 on      # PCI Express Port 10
+		device ref pcie_rp10	on
 			# PCI Express Root port #10 x1, Clock 2 (WLAN)
 			register "PcieRpEnable[9]" = "1"
 			register "PcieRpLtrEnable[9]" = "0"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
-		device pci 1d.4 on      # PCI Express Port 13
+		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
 			register "PcieRpEnable[12]" = "1"
 			register "PcieRpLtrEnable[12]" = "1"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
 		end
-		device pci 1f.3 on      # Intel HDA
+		device ref hda		on
 			register "PchHdaAudioLinkDmic0" = "1"
 			register "PchHdaAudioLinkDmic1" = "1"
 		end
diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
index 9c747cf180..9170671c6b 100644
--- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
@@ -4,7 +4,7 @@ chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1403 inherit
 
-		device pci 14.0 on      # USB xHCI
+		device ref xhci		on
 			register "usb2_ports" = "{
 				[0] = USB2_PORT_MID(OC_SKIP),		/* Type-A port 1 */
 				[1] = USB2_PORT_MID(OC_SKIP),		/* 3G / LTE */
@@ -22,16 +22,16 @@ chip soc/intel/cannonlake
 				[5] = USB3_PORT_EMPTY,			/* Used by TBT */
 			}"
 		end
-		device pci 15.0 on      # I2C #0
+		device ref i2c0		on
 			# I2C HID not supported on galp4
 		end
-		device pci 17.0 on      # SATA
+		device ref sata		on
 			register "SataPortsEnable" = "{
 				[0] = 1,
 				[2] = 1,
 			}"
 		end
-		device pci 1c.4 on      # PCI Express Port 5
+		device ref pcie_rp5	on
 			# PCI Express Root port #5 x4, Clock 4 (TBT)
 			register "PcieRpEnable[4]" = "1"
 			register "PcieRpLtrEnable[4]" = "1"
@@ -39,28 +39,28 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[4]" = "4"
 			register "PcieClkSrcClkReq[4]" = "4"
 		end
-		device pci 1d.0 on      # PCI Express Port 9
+		device ref pcie_rp9	on
 			# PCI Express Root port #9 x1, Clock 3 (LAN)
 			register "PcieRpEnable[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "1"
 			register "PcieClkSrcUsage[3]" = "8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
-		device pci 1d.1 on      # PCI Express Port 10
+		device ref pcie_rp10	on
 			# PCI Express Root port #10 x1, Clock 2 (WLAN)
 			register "PcieRpEnable[9]" = "1"
 			register "PcieRpLtrEnable[9]" = "0"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
-		device pci 1d.4 on      # PCI Express Port 13
+		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
 			register "PcieRpEnable[12]" = "1"
 			register "PcieRpLtrEnable[12]" = "1"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
 		end
-		device pci 1f.3 on      # Intel HDA
+		device ref hda		on
 			register "PchHdaAudioLinkDmic0" = "1"
 			register "PchHdaAudioLinkDmic1" = "1"
 		end
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
index 2279cb33cb..effe2805fe 100644
--- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
@@ -4,7 +4,7 @@ chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1401 inherit
 
-		device pci 14.0 on      # USB xHCI
+		device ref xhci		on
 			register "usb2_ports" = "{
 				[0] = USB2_PORT_MID(OC_SKIP),		/* Type-A port 1 */
 				[1] = USB2_PORT_TYPE_C(OC_SKIP),	/* Type-C port 2 */
@@ -18,7 +18,7 @@ chip soc/intel/cannonlake
 				[2] = USB3_PORT_DEFAULT(OC_SKIP),	/* Type-A port 3 */
 			}"
 		end
-		device pci 15.0 on # I2C #0
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN040D""
 				register "generic.desc" = ""ELAN Touchpad""
@@ -28,7 +28,7 @@ chip soc/intel/cannonlake
 				device i2c 15 on end
 			end
 		end
-		device pci 17.0 on      # SATA
+		device ref sata		on
 			register "SataSalpSupport" = "1"
 			register "SataPortsEnable" = "{
 				[1] = 1, /* Port 2 (J_SSD2) */
@@ -39,7 +39,7 @@ chip soc/intel/cannonlake
 				[2] = 1, /* Port 3 (J_SSD1) */
 			}"
 		end
-		device pci 1c.5 on      # PCI Express Port 6
+		device ref pcie_rp6	on
 			device pci 00.0 on end # x1 Card reader
 			register "PcieRpEnable[5]" = "1"
 			register "PcieRpLtrEnable[5]" = "1"
@@ -47,7 +47,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[3]" = "3"
 			register "PcieRpSlotImplemented[5]" = "1"
 		end
-		device pci 1c.7 on      # PCI Express Port 8
+		device ref pcie_rp8	on
 			device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
 			register "PcieRpEnable[7]" = "1"
 			register "PcieRpLtrEnable[7]" = "1"
@@ -59,7 +59,7 @@ chip soc/intel/cannonlake
 			end
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
-		device pci 1d.0 on      # PCI Express Port 9
+		device ref pcie_rp9	on
 			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
 			register "PcieRpEnable[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "1"
@@ -68,7 +68,7 @@ chip soc/intel/cannonlake
 			register "PcieRpSlotImplemented[8]" = "1"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
-		device pci 1d.4 on      # PCI Express Port 13
+		device ref pcie_rp13	on
 			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
 			register "PcieRpEnable[12]" = "1"
 			register "PcieRpLtrEnable[12]" = "1"