diff options
| author | Tim Crawford <tcrawford@system76.com> | 2023-07-31 14:15:27 -0600 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-08-05 16:09:27 +0000 |
| commit | 1d3e6eba02b074cf02615037694563db8854d3f1 (patch) | |
| tree | 54fc4bc4e6d5e4d426a4facf2fe2ebf38f7719a0 /src/mainboard/system76/adl | |
| parent | c9f99e5632f08f91cc23a96eef54f573078155bc (diff) | |
mb/system76: Enable C10 reporting on systems using eSPI
Report CPU C10 state over eSPI so that the EC can use Virtual Wires to
detect if PECI can be used.
Change-Id: I301361f35caee8ba1c3fd9227219603897add92b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76910
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/system76/adl')
| -rw-r--r-- | src/mainboard/system76/adl/ramstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/system76/adl/ramstage.c b/src/mainboard/system76/adl/ramstage.c index c767f2dfe6..aa9a1b76a7 100644 --- a/src/mainboard/system76/adl/ramstage.c +++ b/src/mainboard/system76/adl/ramstage.c @@ -17,6 +17,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 params->SataPortsSolidStateDrive[1] = 1; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } static void mainboard_init(void *chip_info) |