diff options
| author | Tim Crawford <tcrawford@system76.com> | 2023-07-19 08:21:15 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-25 19:47:36 +0000 |
| commit | 80d54498560dc2c8fb03b7fbd755364eb2fd94c7 (patch) | |
| tree | 0d0e4d6690a5c473e8e2c4f6116ecf72ae6c1a77 /src/mainboard/system76/adl | |
| parent | e56c738f323c72574444152dc5365a8feec52118 (diff) | |
mb/system76/adl: gaze17,oryp10: Remove RTD3 configs
These boards do not actually support RTD3. The power GPIOs for
components are connected to 3.3V and the reset GPIO is connected to
`PLT_RST#`.
Change-Id: Id5e318c388f669d6b2935dc98ae29485955e6e72
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard/system76/adl')
3 files changed, 0 insertions, 67 deletions
diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb index 174c9260cc..6624227537 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb @@ -97,14 +97,6 @@ chip soc/intel/alderlake .clk_req = 1, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - # XXX: Enable tied to 3.3VS? - #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "disable_l23" = "true" - register "srcclk_pin" = "1" # SSD1_CLKREQ# - device generic 0 on end - end end device ref pcie_rp9 on # PCIe RP#9 x1, Clock 6 (GLAN) @@ -113,13 +105,6 @@ chip soc/intel/alderlake .clk_req = 6, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - # XXX: Enable tied to VDD3? - #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "6" # GLAN_CLKREQ# - device generic 0 on end - end end device ref pcie_rp10 on # PCIe RP#10 x1, Clock 2 (WLAN) @@ -128,12 +113,6 @@ chip soc/intel/alderlake .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "2" # WLAN_CLKREQ# - device generic 0 on end - end end device ref pcie_rp11 on # PCIe RP#11 x1, Clock 5 (CARD) @@ -142,13 +121,6 @@ chip soc/intel/alderlake .clk_req = 5, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - # XXX: Enable tied to 3.3VS? - #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "5" # CARD_CLKREQ# - device generic 0 on end - end end end end diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb index a489bf2370..213fa64b3e 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb @@ -103,12 +103,6 @@ chip soc/intel/alderlake .clk_req = 2, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "2" # WLAN_CLKREQ# - device generic 0 on end - end end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 5 (CARD) @@ -117,12 +111,6 @@ chip soc/intel/alderlake .clk_req = 5, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - # XXX: No enable_gpio = no D3cold? - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "5" # CARD_CLKREQ# - device generic 0 on end - end end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 6 (GLAN) @@ -141,14 +129,6 @@ chip soc/intel/alderlake .clk_req = 1, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - # XXX: Enable tied to 3.3VS? - #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "disable_l23" = "true" # Fixes suspend on WD drives - register "srcclk_pin" = "1" # SSD_CLKREQ# - device generic 0 on end - end end device ref gbe on end end diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb index ad75a13611..b675cb4549 100644 --- a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb @@ -146,12 +146,6 @@ chip soc/intel/alderlake .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "2" # WLAN_CLKREQ# - device generic 0 on end - end end device ref pcie_rp6 on # PCIe RP#6 x1, Clock 6 (CARD) @@ -160,12 +154,6 @@ chip soc/intel/alderlake .clk_req = 6, .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - # XXX: Enable connected directly to 3.3VS? - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "6" # CARD_CLKREQ# - device generic 0 on end - end end device ref pcie_rp8 on # PCIe RP#8 x1, Clock 5 (GLAN) @@ -174,13 +162,6 @@ chip soc/intel/alderlake .clk_req = 5, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - # XXX: Enable connected directly to VDD3? - #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "5" # GLAN_CLKREQ# - device generic 0 on end - end end device ref pmc hidden |