Intel i5000 board & chips: Remove - using LATE_CBMEM_INIT

All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
northbridge/intel/i5000

Mainboards:
mainboard/supermicro/x7db8
mainboard/asus/dsbf

Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

7 files changed, 0 insertions, 520 deletions

diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig
deleted file mode 100644
index fd71254cb1..0000000000
--- a/src/mainboard/supermicro/x7db8/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-if BOARD_SUPERMICRO_X7DB8
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_SOCKET_LGA771
-	select SOUTHBRIDGE_INTEL_I3100
-	select NORTHBRIDGE_INTEL_I5000
-	select SUPERIO_WINBOND_W83627HF
-	select BOARD_ROMSIZE_KB_512
-	select HAVE_PIRQ_TABLE
-	select DRIVERS_I2C_W83793
-	select DRIVERS_GENERIC_IOAPIC
-
-config MAINBOARD_DIR
-	string
-	default supermicro/x7db8
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "X7DB8 / X7DB8+"
-
-config MMCONF_BASE_ADDRESS
-	hex
-	default 0xe0000000
-
-config IRQ_SLOT_COUNT
-	int
-	default 48
-
-config MAX_CPUS
-	int
-	default 8
-
-endif
diff --git a/src/mainboard/supermicro/x7db8/Kconfig.name b/src/mainboard/supermicro/x7db8/Kconfig.name
deleted file mode 100644
index b964bcf8ee..0000000000
--- a/src/mainboard/supermicro/x7db8/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUPERMICRO_X7DB8
-	bool "X7DB8 / X7DB8+"
diff --git a/src/mainboard/supermicro/x7db8/board_info.txt b/src/mainboard/supermicro/x7db8/board_info.txt
deleted file mode 100644
index fee61ac577..0000000000
--- a/src/mainboard/supermicro/x7db8/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Category: server
-Board URL: http://www.supermicro.com/products/motherboard/xeon1333/5000p/x7db8_.cfm
-ROM package: PLCC32
-ROM protocol: FWH
-ROM socketed: y
diff --git a/src/mainboard/supermicro/x7db8/cmos.layout b/src/mainboard/supermicro/x7db8/cmos.layout
deleted file mode 100644
index 6f5898e171..0000000000
--- a/src/mainboard/supermicro/x7db8/cmos.layout
+++ /dev/null
@@ -1,104 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007-2008 coresystems GmbH
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; version 2 of
-# the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-#409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-
-# coreboot config options: bootloader
-416        512       s       0        boot_devices
-928          8       h       0        boot_default
-936          1       e       8        cmos_defaults_loaded
-937          1       e       1        lpt
-#938         46       r       0        unused
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     1     Emergency
-6     2     Alert
-6     3     Critical
-6     4     Error
-6     5     Warning
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-8     0     No
-8     1     Yes
-9     0	    Secondary
-9     1	    Primary
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb
deleted file mode 100644
index d496206a16..0000000000
--- a/src/mainboard/supermicro/x7db8/devicetree.cb
+++ /dev/null
@@ -1,177 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/intel/i5000
-
-	device cpu_cluster 0 on
-		chip cpu/intel/socket_LGA771
-			device lapic 0 on end
-		end
-	end
-
-	device domain 0 on
-		device pci 00.0 on # Host bridge
-			subsystemid 0x15d9 0x2017
-		end
-
-		device pci 02.0 on # PCI Express x8 Port 2-3
-			ioapic_irq 8 INTA 0x10
-			ioapic_irq 8 INTB 0x11
-			ioapic_irq 8 INTC 0x12
-			ioapic_irq 8 INTD 0x13
-			device pci 00.0 on # PCI Express Upstream Port
-				device pci 00.0 on # PCI Express Downstream Port E1
-					device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A
-					       ioapic_irq 8 INTA 0x11
-					       ioapic_irq 8 INTB 0x10
-					       ioapic_irq 8 INTC 0x11
-					       ioapic_irq 8 INTD 0x10
-						# PCI slot
-						device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B
-							# PCI slot
-						end
-						device pci 02.0 on # Adaptec U320 #1
-							ioapic_irq 8 INTA 0x10
-						end
-						device pci 02.1 on # Adaptec U320 #2
-							ioapic_irq 8 INTB 0x11
-						end
-					end
-				end
-			device pci 00.1 on end
-			device pci 00.3 on end
-		end
-
-		device pci 03.0 on end
-		device pci 04.0 on end
-		device pci 05.0 on end
-		device pci 06.0 on end
-		device pci 07.0 on end
-			device pci 00.3 on # PCI Express to PCI-X Bridge
-			       ioapic_irq 9 INTA 3
-			       ioapic_irq 9 INTB 0
-			       ioapic_irq 9 INTC 1
-			       ioapic_irq 9 INTD 2
-				# PCI-X Slot
-			end
-		end
-
-		device pci 03.0 on
-			ioapic_irq 8 INTA 0x10
-		end
-		device pci 04.0 on
-			ioapic_irq 8 INTA 0x10
-		end
-		device pci 05.0 on
-			ioapic_irq 8 INTA 0x10
-		end
-		device pci 06.0 on
-			ioapic_irq 8 INTA 0x10
-		end
-		device pci 07.0 on
-			ioapic_irq 8 INTA 0x10
-		end
-
-		device pci 10.0 on end # FBD
-		device pci 10.1 on end # FBD
-		device pci 10.2 on end # FBD
-		device pci 11.0 on end # FBD reserved
-		device pci 13.0 on end # FBD reserved
-		device pci 15.0 on end # FBD
-		device pci 16.0 on end # FBD
-
-		chip southbridge/intel/i3100
-			register "pirq_a_d" = "0x0b0b0b0b"
-			register "pirq_e_h" = "0x80808080"
-			register "sata_ports_implemented" = "0x3f"
-
-			device pci 1c.0 on
-				ioapic_irq 8 INTA 0x14
-				ioapic_irq 8 INTB 0x15
-				ioapic_irq 8 INTC 0x16
-				ioapic_irq 8 INTD 0x17
-			end # PCIe bridge
-			device pci 1d.0 on
-				ioapic_irq 8 INTA 0x10
-			end # USB UHCI
-			device pci 1d.1 on
-				ioapic_irq 8 INTB 0x11
-			end # USB UHCI
-			device pci 1d.2 on
-				ioapic_irq 8 INTC 0x12
-			end # USB UHCI
-			device pci 1d.3 on
-				ioapic_irq 8 INTD 0x13
-			end # USB UHCI
-			device pci 1d.7 on end # USB2 EHCI
-			device pci 1e.0 on
-				device pci 01.0 on end
-			end
-
-			device pci 1f.0 on # PCI-LPC bridge
-				ioapic_irq 8 INTA 0x11
-				subsystemid 0x15d9 0x2009
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off end # FDC
-					device pnp 2e.1 on # Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.2 on # Serial Port 1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-
-					device pnp 2e.3 off end
-					device pnp 2e.5 on # KBC
-					       io 0x60 = 0x60
-					       io 0x62 = 0x64
-					       irq 0x70 = 1
-					       irq 0x72 = 12
-					end
-
-					device pnp 2e.6 off end # CIR
-					device pnp 2e.7 off end # Game port / MIDI
-					device pnp 2e.8 off end # GPIO2
-					device pnp 2e.9 on end # GPIO3
-					device pnp 2e.a on end # ACPI
-					device pnp 2e.b off end # HWMON
-				end
-			end
-			device pci 1f.1 off end # IDE
-			device pci 1f.2 on end # SATA
-			device pci 1f.3 on
-				chip drivers/i2c/w83793
-					register "mfc" = "0x28"
-					register "fanin" = "0x1f"
-					register "peci_agent_conf" = "0x33"
-					register "tcase0" = "0x5e"
-					register "tcase1" = "0x5e"
-					register "tcase2" = "0x5e"
-					register "tcase3" = "0x5e"
-					register "tr_enable" = "0x01"
-					register "critical_temperature" = "0x7f"
-					register "td1_fan_select" = "0x01"
-					register "td2_fan_select" = "0x01"
-					register "td3_fan_select" = "0x01"
-					register "td4_fan_select" = "0x01"
-					device i2c 0x2f on end
-				end
-			end # SMBUS
-		end
-	end
-end
diff --git a/src/mainboard/supermicro/x7db8/irq_tables.c b/src/mainboard/supermicro/x7db8/irq_tables.c
deleted file mode 100644
index 9a2e09d256..0000000000
--- a/src/mainboard/supermicro/x7db8/irq_tables.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
-	PIRQ_VERSION,		/* u16 version */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,		/* Max. number of devices on the bus */
-	0x00,			/* Interrupt router bus */
-	(0x1f << 3) | 0x0,	/* Interrupt router dev */
-	0,			/* IRQs devoted exclusively to PCI usage */
-	0x8086,			/* Vendor */
-	0x2670,			/* Device */
-	0,			/* Miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0,			/* Checksum (has to be set to some value that
-				 * would give 0 after the sum of all bytes
-				 * for this structure (including checksum).
-				 */
-	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
-		{0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
-		{0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
-		{0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
-		{0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
-		{0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
-		{0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
-		{0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
-		{0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
-		{0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
-		{0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c
deleted file mode 100644
index ac8da6d8a6..0000000000
--- a/src/mainboard/supermicro/x7db8/romstage.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <lib.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <northbridge/intel/i5000/raminit.h>
-#include <northbridge/intel/i3100/i3100.h>
-#include <southbridge/intel/i3100/i3100.h>
-#include <southbridge/intel/i3100/early_smbus.c>
-
-#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
-#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-
-#define RCBA_RPC   0x0224 /* 32 bit */
-#define RCBA_HPTC  0x3404 /* 32 bit */
-#define RCBA_GCS   0x3410 /* 32 bit */
-#define RCBA_FD    0x3418 /* 32 bit */
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void early_config(void)
-{
-	u32 gcs, rpc, fd;
-
-	/* Enable RCBA */
-	pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-
-	/* Disable watchdog */
-	gcs = read32(DEFAULT_RCBA + RCBA_GCS);
-	gcs |= (1 << 5); /* No reset */
-	write32(DEFAULT_RCBA + RCBA_GCS, gcs);
-
-	/* Configure PCIe port B as 4x */
-	rpc = read32(DEFAULT_RCBA + RCBA_RPC);
-	rpc |= (3 << 0);
-	write32(DEFAULT_RCBA + RCBA_RPC, rpc);
-
-	/* Disable Modem, Audio, PCIe ports 2/3/4 */
-	fd = read32(DEFAULT_RCBA + RCBA_FD);
-	fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
-	write32(DEFAULT_RCBA + RCBA_FD, fd);
-
-	/* Enable HPET */
-	write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
-
-	/* Setup sata mode */
-	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);
-}
-
-#define DEFAULT_GPIOBASE 0x1180
-static void setup_gpio(void)
-{
-	pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1);
-	pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));
-
-	outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
-	outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
-	outl(0x65b70000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
-	outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
-	outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
-	outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
-	outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */
-}
-
-static void i5000_lpc_config(void)
-{
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
-}
-
-int mainboard_set_fbd_clock(int speed)
-{
-	switch(speed) {
-		case 533:
-			smbus_write_byte(0x6f, 0x80, 0x21);
-			return 0;
-		case 667:
-			smbus_write_byte(0x6f, 0x80, 0x23);
-			return 0;
-		default:
-			printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed);
-			die("");
-			return -1;
-	}
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	if (bist == 0)
-		enable_lapic();
-
-	i5000_lpc_config();
-
-	winbond_enable_serial(SERIAL_DEV, 0x3f8);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	early_config();
-
-	setup_gpio();
-
-	enable_smbus();
-
-	outb(0x07, 0x11b8);
-
-	/* These are smbus write captured with serialice. They
-	   seem to setup the clock generator */
-
-	smbus_write_byte(0x6f, 0x88, 0x1f);
-	smbus_write_byte(0x6f, 0x81, 0xff);
-	smbus_write_byte(0x6f, 0x82, 0xff);
-	smbus_write_byte(0x6f, 0x80, 0x23);
-
-	outb(0x03, 0x11b8);
-	outb(0x01, 0x11b8);
-
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
-	i5000_fbdimm_init();
-	smbus_write_byte(0x69, 0x01, 0x01);
-}