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authorArthur Heymans <arthur@aheymans.xyz>2022-11-12 14:51:49 +0100
committerPaul Fagerburg <pfagerburg@chromium.org>2023-02-04 01:42:39 +0000
commitb5df65a9aaee50421913ace6d7a4b35e0ddff676 (patch)
treeaa885e29c4e724f4fb583bca5c93fe1243e95da2 /src/mainboard/supermicro
parent9ce7935b490830a709c62e271bf269801520ec29 (diff)
mb/*: Replace SNB PCI devices with references from chipset.cb
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/x9sae/devicetree.cb56
-rw-r--r--src/mainboard/supermicro/x9scl/devicetree.cb54
2 files changed, 55 insertions, 55 deletions
diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb
index ed011c1b8d..12cbbaff3b 100644
--- a/src/mainboard/supermicro/x9sae/devicetree.cb
+++ b/src/mainboard/supermicro/x9sae/devicetree.cb
@@ -10,11 +10,11 @@ chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x15d9 0x0644 inherit
- device pci 00.0 on end # Host bridge
- device pci 01.0 on end # CPU1 SLOT6 (x8 or x16)
- device pci 01.1 on end # CPU1 SLOT4 (electrical x8 in x16 if present)
- device pci 02.0 on end # iGPU
- device pci 06.0 on end # CPU1 SLOT7 (electrical x4 in x8)
+ device ref host_bridge on end # Host bridge
+ device ref peg10 on end # CPU1 SLOT6 (x8 or x16)
+ device ref peg11 on end # CPU1 SLOT4 (electrical x8 in x16 if present)
+ device ref igd on end # iGPU
+ device ref peg60 on end # CPU1 SLOT7 (electrical x4 in x8)
chip southbridge/intel/bd82x6x
register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff)
@@ -26,29 +26,29 @@ chip northbridge/intel/sandybridge
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
- device pci 14.0 on end # xHCI
- device pci 16.0 on end # MEI #1
- device pci 16.1 off end # MEI #2
- device pci 16.2 off end # ME IDE-R
- device pci 16.3 off end # ME KT
- device pci 19.0 on end # Intel GbE LAN1
- device pci 1a.0 on end # EHCI #2
- device pci 1b.0 on end # HD Audio
+ device ref xhci on end # xHCI
+ device ref mei1 on end # MEI #1
+ device ref mei2 off end # MEI #2
+ device ref me_ide_r off end # ME IDE-R
+ device ref me_kt off end # ME KT
+ device ref gbe on end # Intel GbE LAN1
+ device ref ehci2 on end # EHCI #2
+ device ref hda on end # HD Audio
- device pci 1c.0 on end # RP #1 PCH SLOT2
- device pci 1c.1 off end # RP #2
- device pci 1c.2 off end # RP #3
- device pci 1c.3 off end # RP #4
- device pci 1c.4 on end # RP #5 PCH SLOT3
- device pci 1c.5 off end # RP #6
- device pci 1c.6 on end # RP #7 PCH SLOT5
- device pci 1c.7 on # RP #8
+ device ref pcie_rp1 on end # RP #1 PCH SLOT2
+ device ref pcie_rp2 off end # RP #2
+ device ref pcie_rp3 off end # RP #3
+ device ref pcie_rp4 off end # RP #4
+ device ref pcie_rp5 on end # RP #5 PCH SLOT3
+ device ref pcie_rp6 off end # RP #6
+ device ref pcie_rp7 on end # RP #7 PCH SLOT5
+ device ref pcie_rp8 on # RP #8
device pci 00.0 on end # 574 GbE LAN2
end
- device pci 1d.0 on end # EHCI #1
- device pci 1e.0 on end # PCI bridge
- device pci 1f.0 on # LPC bridge
+ device ref ehci1 on end # EHCI #1
+ device ref pci_bridge on end # PCI bridge
+ device ref lpc on # LPC bridge
chip superio/nuvoton/nct6776
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off end # Parallel port
@@ -108,10 +108,10 @@ chip northbridge/intel/sandybridge
device pnp c31.0 on end # TPM
end
end
- device pci 1f.2 on end # SATA (AHCI)
- device pci 1f.3 on end # SMBus
- device pci 1f.5 off end # SATA (Legacy)
- device pci 1f.6 off end # Thermal
+ device ref sata1 on end # SATA (AHCI)
+ device ref smbus on end # SMBus
+ device ref sata2 off end # SATA (Legacy)
+ device ref thermal off end # Thermal
end
end
end
diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb
index b0f3534033..e20aac28c2 100644
--- a/src/mainboard/supermicro/x9scl/devicetree.cb
+++ b/src/mainboard/supermicro/x9scl/devicetree.cb
@@ -1,11 +1,11 @@
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x15d9 0x0624 inherit
- device pci 00.0 on end # Host bridge
- device pci 01.0 on end # PEG
- device pci 01.1 on end # PEG
- device pci 02.0 off end # iGPU
- device pci 06.0 on end # PEG
+ device ref host_bridge on end # Host bridge
+ device ref peg10 on end # PEG
+ device ref peg11 on end # PEG
+ device ref igd off end # iGPU
+ device ref peg60 on end # PEG
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff)
register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff)
@@ -16,32 +16,32 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x3f"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 19.0 on # Intel Gigabit Ethernet (not for X9SCL+-F)
+ device ref mei1 off end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+ device ref me_kt off end # Management Engine KT
+ device ref gbe on # Intel Gigabit Ethernet (not for X9SCL+-F)
subsystemid 0x15d9 0x1502
end
- device pci 1a.0 on end # USB2 EHCI #2
- device pci 1b.0 off end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 on # PCIe Port #5
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda off end # High Definition Audio
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 off end # PCIe Port #2
+ device ref pcie_rp3 off end # PCIe Port #3
+ device ref pcie_rp4 off end # PCIe Port #4
+ device ref pcie_rp5 on # PCIe Port #5
device pci 00.0 on end # primary 574 GigE
end
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 on # PCIe Port #7
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 on # PCIe Port #7
device pci 00.0 on end # secondary 574 GigE on X9SCL+-F
end
- device pci 1c.7 off end # PCIe Port #8
- device pci 1d.0 on end # USB2 EHCI #1
- device pci 1e.0 on # PCI bridge
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref ehci1 on end # USB2 EHCI #1
+ device ref pci_bridge on # PCI bridge
device pci 03.0 on end # Matrox G200e in BMC
end
- device pci 1f.0 on # LPC bridge
+ device ref lpc on # LPC bridge
chip superio/nuvoton/nct6776
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off end # Parallel port
@@ -105,10 +105,10 @@ chip northbridge/intel/sandybridge
device pnp 164e.6 off end
end
end
- device pci 1f.2 on end # SATA Controller 1
- device pci 1f.3 on end # SMBus
- device pci 1f.5 off end # SATA Controller 2
- device pci 1f.6 off end # Thermal
+ device ref sata1 on end # SATA Controller 1
+ device ref smbus on end # SMBus
+ device ref sata2 off end # SATA Controller 2
+ device ref thermal off end # Thermal
end
end
end