diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-08-11 17:35:02 +0000 |
---|---|---|
committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-08-11 17:35:02 +0000 |
commit | b339e10f04869a3d8da31e7d52831c32c57302a2 (patch) | |
tree | 9876043ec4255e1dcf619890eba579872273564f /src/mainboard/supermicro | |
parent | 401c8d1da2a5292649498ec3a2c8414bd8ecd62c (diff) |
Enable CBFS everywhere. All boards compiled for me (abuild tested),
and we will fix issues as they appear.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r-- | src/mainboard/supermicro/h8dme/Options.lb | 8 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dai_g/Config.lb | 2 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dai_g/Options.lb | 4 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhe_g/Config.lb | 2 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhe_g/Options.lb | 4 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhe_g2/Config.lb | 2 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhe_g2/Options.lb | 4 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig/Config.lb | 2 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig/Options.lb | 4 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig2/Config.lb | 2 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig2/Options.lb | 4 |
11 files changed, 18 insertions, 20 deletions
diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb index d057f3a562..afb735047a 100644 --- a/src/mainboard/supermicro/h8dme/Options.lb +++ b/src/mainboard/supermicro/h8dme/Options.lb @@ -133,11 +133,9 @@ default CONFIG_MULTIBOOT=0 ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -261,7 +259,7 @@ default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -357,5 +355,5 @@ default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb index 8acd71c724..3e9a87eb77 100644 --- a/src/mainboard/supermicro/x6dai_g/Config.lb +++ b/src/mainboard/supermicro/x6dai_g/Config.lb @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## diff --git a/src/mainboard/supermicro/x6dai_g/Options.lb b/src/mainboard/supermicro/x6dai_g/Options.lb index 73eb826468..2ad1692ea5 100644 --- a/src/mainboard/supermicro/x6dai_g/Options.lb +++ b/src/mainboard/supermicro/x6dai_g/Options.lb @@ -147,7 +147,7 @@ default CONFIG_HEAP_SIZE=0x8000 ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -233,5 +233,5 @@ default CONFIG_CONSOLE_BTEXT=0 # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb index 78be06df0b..2c34ff390d 100644 --- a/src/mainboard/supermicro/x6dhe_g/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g/Config.lb @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture diff --git a/src/mainboard/supermicro/x6dhe_g/Options.lb b/src/mainboard/supermicro/x6dhe_g/Options.lb index 50b3da430e..c9ca49507d 100644 --- a/src/mainboard/supermicro/x6dhe_g/Options.lb +++ b/src/mainboard/supermicro/x6dhe_g/Options.lb @@ -147,7 +147,7 @@ default CONFIG_HEAP_SIZE=0x8000 ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -233,5 +233,5 @@ default CONFIG_CONSOLE_BTEXT=0 # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb index a4950d33ef..722a02077a 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture diff --git a/src/mainboard/supermicro/x6dhe_g2/Options.lb b/src/mainboard/supermicro/x6dhe_g2/Options.lb index 50b3da430e..c9ca49507d 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Options.lb +++ b/src/mainboard/supermicro/x6dhe_g2/Options.lb @@ -147,7 +147,7 @@ default CONFIG_HEAP_SIZE=0x8000 ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -233,5 +233,5 @@ default CONFIG_CONSOLE_BTEXT=0 # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb index 7d70dcf5db..e2d37dc7ca 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## diff --git a/src/mainboard/supermicro/x6dhr_ig/Options.lb b/src/mainboard/supermicro/x6dhr_ig/Options.lb index 199394a28b..717f9df150 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Options.lb +++ b/src/mainboard/supermicro/x6dhr_ig/Options.lb @@ -147,7 +147,7 @@ default CONFIG_HEAP_SIZE=0x8000 ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -232,5 +232,5 @@ default CONFIG_CONSOLE_BTEXT=0 # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb index 4aab4fb04b..566b776c15 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## diff --git a/src/mainboard/supermicro/x6dhr_ig2/Options.lb b/src/mainboard/supermicro/x6dhr_ig2/Options.lb index 199394a28b..717f9df150 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Options.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Options.lb @@ -147,7 +147,7 @@ default CONFIG_HEAP_SIZE=0x8000 ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -232,5 +232,5 @@ default CONFIG_CONSOLE_BTEXT=0 # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end |