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authorVladimir Serbinenko <phcoder@gmail.com>2014-01-03 15:55:40 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-10-16 12:01:10 +0200
commit822bc65b0e8cb9c17721b8b776ec7ecf6ac4129e (patch)
treeb32448affa8d83a08cc4a754aed4731b32c09882 /src/mainboard/supermicro
parent0e64617d7d8adcd4d3db16eed7a34604691c2ee6 (diff)
ACPI: Remove CONFIG_GENERATE_ACPI_TABLES
As currently many systems would be barely functional without ACPI, always generate ACPI tables if supported. Change-Id: I372dbd03101030c904dab153552a1291f3b63518 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4609 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/mptable.c41
1 files changed, 0 insertions, 41 deletions
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index 01a69809d7..84593fcf0d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -107,28 +107,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#if !CONFIG_GENERATE_ACPI_TABLES
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
- /* usb */
- PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
- PCI_INT(0x0, 0x12, 0x1, 0x11);
- PCI_INT(0x0, 0x13, 0x0, 0x12);
- PCI_INT(0x0, 0x13, 0x1, 0x13);
- //PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, 0x16);
-
- /* HD Audio: b0:d20:f1:reg63 should be 0. */
- PCI_INT(0x0, 0x14, 0x2, 0x10);
-
/* on board NIC & Slot PCIE. */
/* configuration B doesnt need dev 5,6,7 */
/*
@@ -149,25 +127,6 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(0)), apicid_sp5100+1, 12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(1)), apicid_sp5100+1, 13); /* card behind dev12 */
- /* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);