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authorAngel Pons <th3fanbus@gmail.com>2020-10-28 18:50:26 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-01-15 11:23:23 +0000
commitba5761a947cc7bd2f13454570e62cde57f4fbd08 (patch)
treee451f8ec6491814d8793558b983adae8cbf8a4d8 /src/mainboard/supermicro
parent6d2d19de7453de04830163a234a970ea9eab386c (diff)
cpu/intel/haswell: Factor out ACPI C-state values
There's no need to have them in the devicetree. ACPI generation can now be simplified even further, and is done in subsequent commits. Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/x10slm-f/devicetree.cb7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb
index 6d64a90221..6cd3ab7933 100644
--- a/src/mainboard/supermicro/x10slm-f/devicetree.cb
+++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb
@@ -4,13 +4,6 @@ chip northbridge/intel/haswell
device cpu_cluster 0 on
chip cpu/intel/haswell
- register "c1_acpower" = "1"
- register "c1_battery" = "1"
- register "c2_acpower" = "3"
- register "c2_battery" = "3"
- register "c3_acpower" = "5"
- register "c3_battery" = "5"
-
device lapic 0 on end
device lapic 0xacac off end
end