diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 10:56:31 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-10 23:08:16 +0000 |
| commit | 8084b3856852f3fb3905e0fe4957b08518095d38 (patch) | |
| tree | c6aca7299eb82c0e6d5a2eba048a3373aa9fe9ca /src/mainboard/supermicro | |
| parent | b92df578b48911893a475b6f47ddfc574f63eac7 (diff) | |
sb/intel/lynxpoint/sata: Always use AHCI mode
The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.
Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/supermicro')
| -rw-r--r-- | src/mainboard/supermicro/x10slm-f/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index ffcc56d15c..6d64a90221 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -26,7 +26,6 @@ chip northbridge/intel/haswell device pci 03.0 off end # Mini-HD audio chip southbridge/intel/lynxpoint - register "sata_ahci" = "1" register "sata_port_map" = "0x3f" register "gen1_dec" = "0x00000295" # Super I/O HWM |