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authorElyes HAOUAS <ehaouas@noos.fr>2019-01-09 08:43:09 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-10 03:14:49 +0000
commit2dce9235244c15efa7c34762a0c47b1fa211ffad (patch)
treefaf7fdd988058c9a1c81dd492802461442b13445 /src/mainboard/supermicro
parent7d1a948fbb0b9b4d5ebc6c06aed272f83c0718c5 (diff)
mb: Move timestamp_add_now to northbridge/amd/amdfam10
Also remove some commented code. Change-Id: If2e91ad871b14b305e2181194d77b100e72f5763 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c3
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c4
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/romstage.c16
3 files changed, 1 insertions, 22 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 838d7e2f09..1834d5da2b 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -235,10 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
- timestamp_add_now(TS_BEFORE_INITRAM);
- printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
- timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 660610eb33..1c049d1192 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -285,10 +285,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
- timestamp_add_now(TS_BEFORE_INITRAM);
- printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
- timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 23d47b4e2f..8508189cc4 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -206,29 +206,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
- printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
- timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
-/*
- dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
-*/
-
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-// die("After MCT init before CAR disabled.");
-
sr5650_before_pci_init();
sb7xx_51xx_before_pci_init();