This drops the ASSEMBLY define from romstage.c, too

(since it's not assembly code, this was a dirty hack anyways)
Also run 
    awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
    mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c 
cut some holes into the source.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

9 files changed, 5 insertions, 41 deletions

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index f341678339..a9c3ef4afa 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -16,9 +16,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 0aed8b9c75..552098d230 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
@@ -77,7 +74,6 @@
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -135,7 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 1221f38f5c..068e27f16d 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define FAM10_SCAN_PCI_BUS 0
@@ -70,7 +67,6 @@
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -126,7 +122,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -194,7 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         console_init();
   printk(BIOS_DEBUG, "\n");
 
-
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
@@ -293,7 +287,6 @@ post_code(0x3E);
 
 post_code(0x40);
 
-
  printk(BIOS_DEBUG, "raminit_amdmct()\n");
  raminit_amdmct(sysinfo);
  post_code(0x41);
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index a9af4b57f4..a65fd34456 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define FAM10_SCAN_PCI_BUS 0
@@ -71,7 +68,6 @@
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -130,7 +126,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -337,7 +332,6 @@ post_code(0x3E);
 
 post_code(0x40);
 
-
  printk(BIOS_DEBUG, "raminit_amdmct()\n");
  raminit_amdmct(sysinfo);
  post_code(0x41);
diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index 8fc496773e..0b274c1947 100644
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -24,7 +22,6 @@
 #include "northbridge/intel/e7525/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -55,7 +52,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/e7525/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -139,3 +135,4 @@ static void main(unsigned long bist)
 	}
 #endif
 }
+
diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index 9d5d8af506..5cbb83074e 100644
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -25,7 +23,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -56,7 +53,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -150,3 +146,4 @@ static void main(unsigned long bist)
 	}
 #endif
 }
+
diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index 0f1041013d..4af2a54131 100644
--- a/src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -25,7 +23,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -56,7 +53,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -151,3 +147,4 @@ static void main(unsigned long bist)
 	}
 #endif
 }
+
diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 4c4f2f19ac..7ddb2c46d7 100644
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -25,7 +23,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -57,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -152,3 +148,4 @@ static void main(unsigned long bist)
 	}
 #endif
 }
+
diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index 8e46e928fe..38c06d5000 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -25,7 +23,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -57,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -152,3 +148,4 @@ static void main(unsigned long bist)
 	}
 #endif
 }
+