diff options
author | Martin Roth <gaumless@gmail.com> | 2017-10-15 14:58:49 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:24:53 +0000 |
commit | f6af8943e23b8ffa27df6ddb8e4a654387be0cb6 (patch) | |
tree | d5b2cab4d1ba2b8de91fd1abedf07033a429b19a /src/mainboard/supermicro/x7db8/romstage.c | |
parent | 779b32beffae83ece727a43f2ce216513bf66c15 (diff) |
Intel i5000 board & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i5000
Mainboards:
mainboard/supermicro/x7db8
mainboard/asus/dsbf
Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro/x7db8/romstage.c')
-rw-r--r-- | src/mainboard/supermicro/x7db8/romstage.c | 145 |
1 files changed, 0 insertions, 145 deletions
diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c deleted file mode 100644 index ac8da6d8a6..0000000000 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <lib.h> -#include <console/console.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> -#include <northbridge/intel/i5000/raminit.h> -#include <northbridge/intel/i3100/i3100.h> -#include <southbridge/intel/i3100/i3100.h> -#include <southbridge/intel/i3100/early_smbus.c> - -#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) -#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) - -#define RCBA_RPC 0x0224 /* 32 bit */ -#define RCBA_HPTC 0x3404 /* 32 bit */ -#define RCBA_GCS 0x3410 /* 32 bit */ -#define RCBA_FD 0x3418 /* 32 bit */ - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -static void early_config(void) -{ - u32 gcs, rpc, fd; - - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - /* Disable watchdog */ - gcs = read32(DEFAULT_RCBA + RCBA_GCS); - gcs |= (1 << 5); /* No reset */ - write32(DEFAULT_RCBA + RCBA_GCS, gcs); - - /* Configure PCIe port B as 4x */ - rpc = read32(DEFAULT_RCBA + RCBA_RPC); - rpc |= (3 << 0); - write32(DEFAULT_RCBA + RCBA_RPC, rpc); - - /* Disable Modem, Audio, PCIe ports 2/3/4 */ - fd = read32(DEFAULT_RCBA + RCBA_FD); - fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); - write32(DEFAULT_RCBA + RCBA_FD, fd); - - /* Enable HPET */ - write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); - - /* Setup sata mode */ - pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); -} - -#define DEFAULT_GPIOBASE 0x1180 -static void setup_gpio(void) -{ - pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); - - outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0x65b70000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ -} - -static void i5000_lpc_config(void) -{ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); -} - -int mainboard_set_fbd_clock(int speed) -{ - switch(speed) { - case 533: - smbus_write_byte(0x6f, 0x80, 0x21); - return 0; - case 667: - smbus_write_byte(0x6f, 0x80, 0x23); - return 0; - default: - printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); - die(""); - return -1; - } -} - -void mainboard_romstage_entry(unsigned long bist) -{ - if (bist == 0) - enable_lapic(); - - i5000_lpc_config(); - - winbond_enable_serial(SERIAL_DEV, 0x3f8); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - early_config(); - - setup_gpio(); - - enable_smbus(); - - outb(0x07, 0x11b8); - - /* These are smbus write captured with serialice. They - seem to setup the clock generator */ - - smbus_write_byte(0x6f, 0x88, 0x1f); - smbus_write_byte(0x6f, 0x81, 0xff); - smbus_write_byte(0x6f, 0x82, 0xff); - smbus_write_byte(0x6f, 0x80, 0x23); - - outb(0x03, 0x11b8); - outb(0x01, 0x11b8); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); - i5000_fbdimm_init(); - smbus_write_byte(0x69, 0x01, 0x01); -} |