diff options
author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-17 02:46:24 +0100 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-18 02:11:06 +0100 |
commit | 5878bbd935c8cbd7c6d25ef72a5460f3262119e7 (patch) | |
tree | 5a8500e6c3d5afbbdf2e54e51f9ef46ad3a4d6d0 /src/mainboard/supermicro/x6dhr_ig2/mptable.c | |
parent | 61ed48c9233e0d74ef5c6847052662d075553691 (diff) |
Drop Intel E7520 and E7525 and related boards
There is no Cache As Ram for these boards, let's get rid of them.
Also drop unused dependencies
Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7836
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/supermicro/x6dhr_ig2/mptable.c')
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig2/mptable.c | 168 |
1 files changed, 0 insertions, 168 deletions
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c deleted file mode 100644 index b5ba6b1ffc..0000000000 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ /dev/null @@ -1,168 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - unsigned char bus_pxhd_1; - unsigned char bus_pxhd_2; - unsigned char bus_pxhd_3; - unsigned char bus_pxhd_4; - unsigned char bus_ich5r_1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - { - device_t dev; - - /* ich5r */ - dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); - if (dev) { - bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - - bus_ich5r_1 = 7; - } - /* pxhd-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); - if (dev) { - bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n"); - - bus_pxhd_1 = 2; - } - /* pxhd-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); - if (dev) { - bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n"); - - bus_pxhd_2 = 3; - } - - /* pxhd-3 */ - dev = dev_find_slot(0, PCI_DEVFN(0x4,0)); - if (dev) { - bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n"); - - bus_pxhd_3 = 5; - } - /* pxhd-4 */ - dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); - if (dev) { - bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n"); - - bus_pxhd_4 = 6; - } - - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - struct resource *res; - device_t dev; - /* pxhd apic 3 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x03, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); - } - /* pxhd apic 4 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x04, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); - } - } - mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); - - /* ISA backward compatibility interrupts */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x76, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x77, 0x02, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x75, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7c, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7d, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x08, 0x03, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0c, 0x03, 0x06); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0d, 0x03, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_2, 0x08, 0x04, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_ich5r_1, 0x04, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_4, 0x00, 0x02, 0x10); -#if 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - (bus_isa - 1), 0x04, 0x02, 0x10); -#endif - /* Standard local interrupt assignments */ -#if 0 - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x00); -#endif - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x01); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} |