mb/supermicro: restructure x11ssh-tf to represent a x11 board series

Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.

There are about 20 boards that can be added, if there is a community for
testing.

To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.

It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").

The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.

X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.

Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.

Documentation is reworked in CB:35547

Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

17 files changed, 0 insertions, 913 deletions

diff --git a/src/mainboard/supermicro/x11ssh/Kconfig b/src/mainboard/supermicro/x11ssh/Kconfig
deleted file mode 100644
index dcf6bb9533..0000000000
--- a/src/mainboard/supermicro/x11ssh/Kconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-config BOARD_SUPERMICRO_BASEBOARD_X11SSH
-	def_bool n
-	select BOARD_ROMSIZE_KB_16384
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select SOC_INTEL_KABYLAKE
-	select SKYLAKE_SOC_PCH_H
-	select MAINBOARD_HAS_LPC_TPM
-	select DRIVERS_ASPEED_AST2050
-	select SUPERIO_ASPEED_AST2400
-	select GENERATE_SMBIOS_TABLES
-	select IPMI_KCS
-
-if BOARD_SUPERMICRO_BASEBOARD_X11SSH
-
-config VBOOT
-	select VBOOT_NO_BOARD_SUPPORT
-	select GBB_FLAG_DISABLE_LID_SHUTDOWN
-	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
-	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
-	select GBB_FLAG_DISABLE_FWMP
-
-config VBOOT_SLOTS_RW_AB
-	default y
-
-config VBOOT_VBNV_OFFSET
-	hex
-	default 0x2a
-
-config FMDFILE
-	string
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB
-
-config CBFS_SIZE
-	hex
-	default 0xb00000
-
-config IRQ_SLOT_COUNT
-	int
-	default 18
-
-config MAINBOARD_DIR
-	string
-	default "supermicro/x11ssh"
-
-config VARIANT_DIR
-	string
-	default "tf" if BOARD_SUPERMICRO_X11SSH_TF
-
-config DEVICETREE
-	string
-	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF
-
-config MAX_CPUS
-	int
-	default 8
-
-config SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config CONSOLE_POST
-	bool
-	default y
-
-config POST_DEVICE
-	bool
-	default n
-
-config DIMM_SPD_SIZE
-	int
-	default 512
-
-endif # BOARD_SUPERMICRO_BASEBOARD_X11SSH
diff --git a/src/mainboard/supermicro/x11ssh/Kconfig.name b/src/mainboard/supermicro/x11ssh/Kconfig.name
deleted file mode 100644
index 43d0517378..0000000000
--- a/src/mainboard/supermicro/x11ssh/Kconfig.name
+++ /dev/null
@@ -1,3 +0,0 @@
-config BOARD_SUPERMICRO_X11SSH_TF
-	bool "X11SSH-TF"
-	select BOARD_SUPERMICRO_BASEBOARD_X11SSH
diff --git a/src/mainboard/supermicro/x11ssh/Makefile.inc b/src/mainboard/supermicro/x11ssh/Makefile.inc
deleted file mode 100644
index a6d789e11c..0000000000
--- a/src/mainboard/supermicro/x11ssh/Makefile.inc
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-## Copyright (C) 2016 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-bootblock-y += bootblock.c
-
-ramstage-y += ramstage.c
-
-subdirs-y += variants/$(VARIANT_DIR)
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/supermicro/x11ssh/acpi/ec.asl b/src/mainboard/supermicro/x11ssh/acpi/ec.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/supermicro/x11ssh/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl b/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl
+++ /dev/null
diff --git a/src/mainboard/supermicro/x11ssh/acpi/superio.asl b/src/mainboard/supermicro/x11ssh/acpi/superio.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/supermicro/x11ssh/acpi/superio.asl
+++ /dev/null
diff --git a/src/mainboard/supermicro/x11ssh/acpi_tables.c b/src/mainboard/supermicro/x11ssh/acpi_tables.c
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/supermicro/x11ssh/acpi_tables.c
+++ /dev/null
diff --git a/src/mainboard/supermicro/x11ssh/board_info.txt b/src/mainboard/supermicro/x11ssh/board_info.txt
deleted file mode 100644
index 029d2a9bbb..0000000000
--- a/src/mainboard/supermicro/x11ssh/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Supermicro
-Board name: X11SSH Baseboard
-Category: server
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/supermicro/x11ssh/bootblock.c b/src/mainboard/supermicro/x11ssh/bootblock.c
deleted file mode 100644
index 8bc8ab00e5..0000000000
--- a/src/mainboard/supermicro/x11ssh/bootblock.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-#include "gpio.h"
-#include <superio/aspeed/common/aspeed.h>
-#include <superio/aspeed/ast2400/ast2400.h>
-#include <delay.h>
-#include <console/uart.h>
-
-static void early_config_gpio(void)
-{
-	/* This is a hack for FSP because it does things in MemoryInit()
-	 * which it shouldn't do. We have to prepare certain gpios here
-	 * because of the brokenness in FSP. */
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
-
-static void early_config_superio(void)
-{
-	const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1);
-	if (CONFIG(CONSOLE_SERIAL)) {
-		aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
-		/* The serial output is garbeled before this timeout.
-		 * FIXME: Find out why and remove delay.
-		 */
-		mdelay(1000);
-	}
-}
-
-void bootblock_mainboard_early_init(void)
-{
-	early_config_gpio();
-	early_config_superio();
-}
diff --git a/src/mainboard/supermicro/x11ssh/cmos.layout b/src/mainboard/supermicro/x11ssh/cmos.layout
deleted file mode 100644
index 201ca3320c..0000000000
--- a/src/mainboard/supermicro/x11ssh/cmos.layout
+++ /dev/null
@@ -1,62 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-#start-bit length  config config-ID    name
-
-0          120       r       0        reserved_memory
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-395          4       e       6        debug_level
-448          128      r      0        vbnv
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     0     Emergency
-6     1     Alert
-6     2     Critical
-6     3     Error
-6     4     Warning
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/supermicro/x11ssh/dsdt.asl b/src/mainboard/supermicro/x11ssh/dsdt.asl
deleted file mode 100644
index ac929a6bc4..0000000000
--- a/src/mainboard/supermicro/x11ssh/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	// Some generic macros
-	#include <soc/intel/skylake/acpi/platform.asl>
-
-	// global NVS and variables
-	#include <soc/intel/skylake/acpi/globalnvs.asl>
-
-	// CPU
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <soc/intel/skylake/acpi/systemagent.asl>
-			#include <soc/intel/skylake/acpi/pch.asl>
-		}
-	}
-
-	// Chipset specific sleep states
-	#include <soc/intel/skylake/acpi/sleepstates.asl>
-
-	// Mainboard specific
-	#include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/supermicro/x11ssh/gpio.h b/src/mainboard/supermicro/x11ssh/gpio.h
deleted file mode 100644
index 02fe90c34d..0000000000
--- a/src/mainboard/supermicro/x11ssh/gpio.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- */
-
-#ifndef _GPIOX11SSHTF_H
-#define _GPIOX11SSHTF_H
-
-#include <soc/gpe.h>
-#include <soc/gpio.h>
-
-#ifndef __ACPI__
-static const struct pad_config gpio_table[] = {
-/* RCIN# */	_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000),
-/* LAD0 */	_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000),
-/* LAD1 */	_PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000),
-/* LAD2 */	_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000),
-/* LAD3 */	_PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000),
-/* LFRAME# */	_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000),
-/* SERIRQ */	_PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000),
-/* PIRQA# */	_PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000),
-/* CLKRUN# */	_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000),
-/* CLKOUT_LPC0 */	_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000),
-/* CLKOUT_LPC1 */	_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000),
-/* PME# */	_PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000),
-/* SUSWARN# */	_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000),
-/* SUS_STAT# */	_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000),
-/* SUS_ACK# */	_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000),
-/* CLKOUT_48 */	_PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000),
-/* RESERVED */	//_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000),
-/* SLP_S0# */	_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000),
-/* PLTRST# */	_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000),
-/* SPKR */	_PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000),
-/* PCHHOT# */	_PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000),
-/* RESERVED */  //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00),
-/* RESERVED */	//_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000),
-/* RESERVED */	//_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00),
-/* RESERVED */	//_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000),
-/* RESERVED */	//_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
-/* RESERVED */	//_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000),
-/* SATAXPCIE0 */	_PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000),
-/* SATA_LED# */	_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000),
-/* USB_OC0# */	_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000),
-/* USB_OC1# */	_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000),
-/* USB_OC2# */	_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000),
-/* USB_OC3# */	_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000),
-/* SATA_SCLOCK */	_PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000),
-/* SATA_SLOAD */	_PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000),
-/* SATA_SDATAOUT1 */	_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000),
-/* SATA_SDATAOUT2 */	_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000),
-/* USB_OC4# */	_PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000),
-/* USB_OC5# */	_PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000),
-/* NMI# */	_PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000),
-/* SMI# */	_PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000),
-/* SRCCLKREQ9# */	_PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000),
-/* SML2CLK */	_PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000),
-/* SML2DATA */	_PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000),
-/* SML3CLK */	_PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000),
-/* SML3DATA */	_PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000),
-/* SML4CLK */	_PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000),
-/* SML4DATA */	_PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000),
-/* LAN_WAKE# */	_PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000),
-/* PWRBTN# */	_PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000),
-/* SLP_S3# */	_PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000),
-/* SLP_S4# */	_PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000),
-/* SLP_A# */	_PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000),
-/* SUSCLK */	_PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000),
-/* DDPB_HPD0 */	_PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000),
-/* DDPC_HPD1 */	_PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000),
-/* DDPD_HPD2 */	_PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000),
-/* DDPE_HPD3 */	_PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000),
-/* GPIO */	_PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000),
-/* DDPB_CTRLCLK */	_PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000),
-/* DDPB_CTRLDATA */	_PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000),
-/* DDPC_CTRLCLK */	_PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000),
-/* DDPC_CTRLDATA */	_PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000),
-/* DDPD_CTRLCLK */	_PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000),
-/* DDPD_CTRLDATA */	_PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000),
-};
-
-
-/*** XXX TODO XXX */
-/* Early pad configuration in romstage. */
-static const struct pad_config early_gpio_table[] = {
-/* LPC */
-
-/* LAD0 */	_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000),
-/* LAD1 */	_PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000),
-/* LAD2 */	_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000),
-/* LAD3 */	_PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000),
-/* LFRAME# */	_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000),
-/* SERIRQ */	_PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000),
-/* CLKRUN# */	_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000),
-/* CLKOUT_LPC0 */	_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000),
-/* CLKOUT_LPC1 */	_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000),
-};
-
-#endif /* __ACPI__ */
-#endif /* _GPIOX11SSHTF_H */
diff --git a/src/mainboard/supermicro/x11ssh/ramstage.c b/src/mainboard/supermicro/x11ssh/ramstage.c
deleted file mode 100644
index a37d2d2430..0000000000
--- a/src/mainboard/supermicro/x11ssh/ramstage.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <bootstate.h>
-#include <soc/ramstage.h>
-#include "gpio.h"
-
-void mainboard_silicon_init_params(FSP_SIL_UPD *params)
-{
-	/* Configure pads prior to SiliconInit() in case there's any
-	 * dependencies during hardware initialization. */
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-
-	/* This must be one, otherwise FSP crashes ... */
-	params->PchHdaVcType = 0x1;
-}
diff --git a/src/mainboard/supermicro/x11ssh/romstage.c b/src/mainboard/supermicro/x11ssh/romstage.c
deleted file mode 100644
index cb1f1059f2..0000000000
--- a/src/mainboard/supermicro/x11ssh/romstage.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <fsp/api.h>
-#include <soc/romstage.h>
-#include <spd_bin.h>
-
-void mainboard_memory_init_params(FSPM_UPD *mupd)
-{
-	FSP_M_CONFIG *mem_cfg;
-	mem_cfg = &mupd->FspmConfig;
-
-	struct spd_block blk = {
-		.addr_map = { 0x50, 0x51, 0x52, 0x53, },
-	};
-
-	mem_cfg->DqPinsInterleaved = 1;
-	get_spd_smbus(&blk);
-	mem_cfg->MemorySpdDataLen = blk.len;
-	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
-	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
-	mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
-	mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
-	mem_cfg->UserBd = BOARD_TYPE_SERVER;
-
-	mupd->FspmTestConfig.DmiVc1 = 1;
-}
diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt b/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt
deleted file mode 100644
index f3eb3ef227..0000000000
--- a/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Supermicro
-Board name: X11SSH-TF
-Category: server
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
deleted file mode 100644
index ce6bfa5fba..0000000000
--- a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
+++ /dev/null
@@ -1,290 +0,0 @@
-chip soc/intel/skylake
-
-	# Enable deep Sx states
-	register "deep_s5_enable_ac" = "0"
-	register "deep_s5_enable_dc" = "0"
-	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_B"
-	register "gpe0_dw1" = "GPP_D"
-	register "gpe0_dw2" = "GPP_E"
-
-	register "gen1_dec" = "0x007c0a01" # Super IO SWC
-	register "gen2_dec" = "0x000c0ca1" # IPMI KCS
-	register "gen3_dec" = "0x000c03e1" # UART3
-	register "gen4_dec" = "0x000c02e1" # UART4
-
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
-	# FSP Configuration
-	register "SmbusEnable" = "1"
-	register "ScsEmmcEnabled" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
-	register "SkipExtGfxScan" = "1"
-	register "Device4Enable" = "1"
-	register "SaGv" = "SaGv_Disabled"
-
-	# Disable SGX
-	register "sgx_enable" = "0" # SGX is broken in coreboot
-	register "PrmrrSize" = "128 * MiB"
-
-	register "pirqa_routing" = "PCH_IRQ11"
-	register "pirqb_routing" = "PCH_IRQ10"
-	register "pirqc_routing" = "PCH_IRQ11"
-	register "pirqd_routing" = "PCH_IRQ11"
-	register "pirqe_routing" = "PCH_IRQ11"
-	register "pirqf_routing" = "PCH_IRQ11"
-	register "pirqg_routing" = "PCH_IRQ11"
-	register "pirqh_routing" = "PCH_IRQ11"
-
-	# SATA configuration
-	register "SataMode" = "0" # AHCI
-	register "EnableSata" = "1"
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable" = "{ \
-		[0]	= 1, \
-		[1]	= 1, \
-		[2]	= 1, \
-		[3]	= 1, \
-		[4]	= 1, \
-		[5]	= 1, \
-		[6]	= 1, \
-		[7]	= 1, \
-	}"
-
-	register "SataPortsDevSlp" = "{\
-		[0]	= 0, \
-		[1]	= 0, \
-		[2]	= 0, \
-		[3]	= 0, \
-		[4]	= 0, \
-		[5]	= 0, \
-		[6]	= 0, \
-		[7]	= 0, \
-	}"
-
-	# superspeed_inter-chip_supplement (SSIC) disabled
-	register "SsicPortEnable" = "0"
-
-	# USB configuration
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2/3
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2/3
-	register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # ?
-	register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # ?
-
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB4/5
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # USB4/5
-
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB0/1
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # USB0/1
-
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
-	register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
-
-	register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
-	register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
-
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # USB8 (USB3.0)
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
-
-	register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB
-
-	# LPC
-	register "serirq_mode" = "SERIRQ_CONTINUOUS"
-
-	# PCIe configuration
-	# Enable JPCIE1
-	register "PcieRpEnable[0]" = "1"
-	register "PcieRpClkReqSupport[0]" = "0"
-
-	# Enable ASpeed PCI bridge
-	register "PcieRpEnable[2]" = "1"
-	register "PcieRpClkReqSupport[2]" = "0"
-
-	# Enable X550T (10GbE)
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpClkReqSupport[4]" = "0"
-
-	# Enable M.2
-	register "PcieRpEnable[8]" = "1"
-	register "PcieRpClkReqSupport[8]" = "0"
-
-	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
-	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
-	register "PmConfigSlpS3MinAssert" = "0x02"
-
-	# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
-	register "PmConfigSlpS4MinAssert" = "0x04"
-
-	# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
-	register "PmConfigSlpSusMinAssert" = "0x03"
-
-	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
-	register "PmConfigSlpAMinAssert" = "0x03"
-
-	# VR Settings Configuration for 4 Domains
-	# ICC_MAX = 0 (Auto)
-	# Voltage limit 1.52V (not used on KBL-S and KBL-DT)
-	# Disable PS4 powerstate in S0ix, thus no package C10 support
-	# psi threshold is using FSP default values
-	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
-		.vr_config_enable = 1, \
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1, \
-		.psi4enable = 0, \
-		.imon_slope = 0x0, \
-		.imon_offset = 0x0, \
-		.icc_max = 0, \
-		.voltage_limit = 1520 \
-	}"
-
-	register "domain_vr_config[VR_IA_CORE]" = "{
-		.vr_config_enable = 1, \
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1, \
-		.psi4enable = 0, \
-		.imon_slope = 0x0, \
-		.imon_offset = 0x0, \
-		.icc_max = 0, \
-		.voltage_limit = 1520 \
-	}"
-
-	register "domain_vr_config[VR_GT_UNSLICED]" = "{
-		.vr_config_enable = 1, \
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1, \
-		.psi4enable = 0, \
-		.imon_slope = 0x0, \
-		.imon_offset = 0x0, \
-		.icc_max = 0 ,\
-		.voltage_limit = 1520 \
-	}"
-
-	register "domain_vr_config[VR_GT_SLICED]" = "{
-		.vr_config_enable = 1, \
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1, \
-		.psi4enable = 0, \
-		.imon_slope = 0x0, \
-		.imon_offset = 0x0, \
-		.icc_max = 0, \
-		.voltage_limit = 1520 \
-	}"
-
-	# No extra VR mailbox command
-	register "SendVrMbxCmd" = "0"
-
-	# Lock Down
-	register "common_soc_config" = "{
-	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
-	}"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-		device pci 00.0 on end # Host Bridge
-		device pci 01.0 on end # unused
-		device pci 01.1 on
-			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
-		end # PCIE Slot (JPCIE1)
-		device pci 04.0 on end # SA thermal subsystem
-		device pci 14.0 on end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 on end # Thermal Subsystem
-		device pci 16.0 on end # Management Engine Interface 1
-		device pci 16.1 on end # Management Engine Interface 2
-		device pci 17.0 on end # SATA
-		device pci 1c.0 on
-			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
-		end # PCI Express Port 1 (Slot JPCIE1)
-		device pci 1c.2 on
-			device pci 00.0 on
-				device pci 00.0 on end # Aspeed 2400 VGA
-			end
-		end # PCI Express Port 3
-		device pci 1c.4 on
-			device pci 00.0 on end # 10GbE
-			device pci 00.1 on end # 10GbE
-		end # PCI Express Port 5
-		device pci 1d.0 on
-			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
-		end # PCI Express Port 9
-		device pci 1f.0 on
-			chip drivers/ipmi
-				# On cold boot it takes a while for the BMC to start the IPMI service
-				register "wait_for_bmc" = "1"
-				register "bmc_boot_timeout" = "60"
-				device pnp ca2.0 on end # IPMI KCS
-			end
-			chip superio/common
-				device pnp 2e.0 on
-					chip superio/aspeed/ast2400
-						device pnp 2e.2 on # SUART1
-							io 0x60 = 0x3f8
-							irq 0x70 = 4
-						end
-						device pnp 2e.3 on # SUART2
-							io 0x60 = 0x2f8
-							irq 0x70 = 3
-						end
-						device pnp 2e.4 on # SWC
-							io 0x60 = 0xa00
-							io 0x62 = 0xa10
-							io 0x64 = 0xa20
-							io 0x66 = 0xa30
-							irq 0x70 = 0xb
-						end
-						device pnp 2e.5 on #  Keyboard
-							io 0x60 = 0x60
-							io 0x62 = 0x64
-							irq 0x70 = 1
-							irq 0x72 = 0xc
-						end
-						device pnp 2e.7 on #  GPIO
-						end
-						device pnp 2e.b on #  SUART3
-							io 0x60 = 0x3e8
-							irq 0x70 = 4
-						end
-						device pnp 2e.c on # SUART4
-							io 0x60 = 0x2e8
-							irq 0x70 = 3
-						end
-						device pnp 2e.d on #  iLPC2AHB
-						end
-						device pnp 2e.e on #  Mailbox
-							io 0x60 = 0xa40
-							irq 0x70 = 0x00
-						end
-					end
-				end
-			end
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end # LPC Interface
-		device pci 1f.1 on end # P2SB
-		device pci 1f.2 on end # Power Management Controller
-		device pci 1f.4 on end # SMBus
-		device pci 1f.5 on end # SPI Controller
-	end
-end
diff --git a/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd
deleted file mode 100644
index a29568072e..0000000000
--- a/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd
+++ /dev/null
@@ -1,36 +0,0 @@
-FLASH 16M {
-	SI_ALL@0x0 0x500000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x4ff000
-	}
-	SI_BIOS@0x500000 0xb00000 {
-		RW_SECTION_A@0x0 0x33e000 {
-			VBLOCK_A@0x0 0x20000
-			FW_MAIN_A(CBFS)@0x20000 0x31dfc0
-			RW_FWID_A@0x33dfc0 0x40
-		}
-		RW_SECTION_B@0x33e000 0x33e000 {
-			VBLOCK_B@0x0 0x20000
-			FW_MAIN_B(CBFS)@0x20000 0x31dfc0
-			RW_FWID_B@0x33dfc0 0x40
-		}
-		MISC_RW@0x67d000 0x62000 {
-			UNIFIED_MRC_CACHE@0x0 0x20000 {
-				RECOVERY_MRC_CACHE@0x0 0x10000
-				RW_MRC_CACHE@0x10000 0x10000
-			}
-			RW_VPD(PRESERVE)@0x20000 0x2000
-			SMMSTORE(PRESERVE)@0x22000 0x40000
-		}
-		WP_RO@0x6df000 0x421000 {
-			RO_VPD(PRESERVE)@0x0 0x4000
-			RO_SECTION@0x4000 0x41d000 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0xef000
-				COREBOOT(CBFS)@0xf0000 0x32d000
-			}
-		}
-	}
-}