mb/supermicro/x11ssh: Add Supermicro X11SSH-TF

Add support for the X11SSH-TF which is based on Intel KBL.

Working:
* SeaBIOS payload
* LinuxBoot payload
* IPMI of BMC
* PCIe, SATA, USB and M.2 ports
* RS232 serial
* Native graphics init

Not working:
* TianoCore doesn't work yet as the Aspeed NGI is text mode only.
* Intel SGX, due to random crashes in soc/intel/common

For more details have a look at the documentation.

Please apply those patches as well for good user experience:

Ica0c20255f661dd61edc3a7d15646b7447c4658e

Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

2 files changed, 296 insertions, 0 deletions

diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt b/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt
new file mode 100644
index 0000000000..f3eb3ef227
--- /dev/null
+++ b/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Supermicro
+Board name: X11SSH-TF
+Category: server
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
new file mode 100644
index 0000000000..ce6bfa5fba
--- /dev/null
+++ b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
@@ -0,0 +1,290 @@
+chip soc/intel/skylake
+
+	# Enable deep Sx states
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "GPP_B"
+	register "gpe0_dw1" = "GPP_D"
+	register "gpe0_dw2" = "GPP_E"
+
+	register "gen1_dec" = "0x007c0a01" # Super IO SWC
+	register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+	register "gen3_dec" = "0x000c03e1" # UART3
+	register "gen4_dec" = "0x000c02e1" # UART4
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# FSP Configuration
+	register "SmbusEnable" = "1"
+	register "ScsEmmcEnabled" = "0"
+	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsSdCardEnabled" = "0"
+	register "SkipExtGfxScan" = "1"
+	register "Device4Enable" = "1"
+	register "SaGv" = "SaGv_Disabled"
+
+	# Disable SGX
+	register "sgx_enable" = "0" # SGX is broken in coreboot
+	register "PrmrrSize" = "128 * MiB"
+
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+	# SATA configuration
+	register "SataMode" = "0" # AHCI
+	register "EnableSata" = "1"
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable" = "{ \
+		[0]	= 1, \
+		[1]	= 1, \
+		[2]	= 1, \
+		[3]	= 1, \
+		[4]	= 1, \
+		[5]	= 1, \
+		[6]	= 1, \
+		[7]	= 1, \
+	}"
+
+	register "SataPortsDevSlp" = "{\
+		[0]	= 0, \
+		[1]	= 0, \
+		[2]	= 0, \
+		[3]	= 0, \
+		[4]	= 0, \
+		[5]	= 0, \
+		[6]	= 0, \
+		[7]	= 0, \
+	}"
+
+	# superspeed_inter-chip_supplement (SSIC) disabled
+	register "SsicPortEnable" = "0"
+
+	# USB configuration
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2/3
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2/3
+	register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # ?
+	register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # ?
+
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB4/5
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # USB4/5
+
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB0/1
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # USB0/1
+
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
+	register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
+
+	register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
+	register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
+
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # USB8 (USB3.0)
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
+
+	register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB
+
+	# LPC
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+	# PCIe configuration
+	# Enable JPCIE1
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpClkReqSupport[0]" = "0"
+
+	# Enable ASpeed PCI bridge
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpClkReqSupport[2]" = "0"
+
+	# Enable X550T (10GbE)
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpClkReqSupport[4]" = "0"
+
+	# Enable M.2
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpClkReqSupport[8]" = "0"
+
+	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+	register "PmConfigSlpS3MinAssert" = "0x02"
+
+	# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+	register "PmConfigSlpS4MinAssert" = "0x04"
+
+	# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+	register "PmConfigSlpSusMinAssert" = "0x03"
+
+	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+	register "PmConfigSlpAMinAssert" = "0x03"
+
+	# VR Settings Configuration for 4 Domains
+	# ICC_MAX = 0 (Auto)
+	# Voltage limit 1.52V (not used on KBL-S and KBL-DT)
+	# Disable PS4 powerstate in S0ix, thus no package C10 support
+	# psi threshold is using FSP default values
+	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+		.vr_config_enable = 1, \
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1, \
+		.psi4enable = 0, \
+		.imon_slope = 0x0, \
+		.imon_offset = 0x0, \
+		.icc_max = 0, \
+		.voltage_limit = 1520 \
+	}"
+
+	register "domain_vr_config[VR_IA_CORE]" = "{
+		.vr_config_enable = 1, \
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1, \
+		.psi4enable = 0, \
+		.imon_slope = 0x0, \
+		.imon_offset = 0x0, \
+		.icc_max = 0, \
+		.voltage_limit = 1520 \
+	}"
+
+	register "domain_vr_config[VR_GT_UNSLICED]" = "{
+		.vr_config_enable = 1, \
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1, \
+		.psi4enable = 0, \
+		.imon_slope = 0x0, \
+		.imon_offset = 0x0, \
+		.icc_max = 0 ,\
+		.voltage_limit = 1520 \
+	}"
+
+	register "domain_vr_config[VR_GT_SLICED]" = "{
+		.vr_config_enable = 1, \
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1, \
+		.psi4enable = 0, \
+		.imon_slope = 0x0, \
+		.imon_offset = 0x0, \
+		.icc_max = 0, \
+		.voltage_limit = 1520 \
+	}"
+
+	# No extra VR mailbox command
+	register "SendVrMbxCmd" = "0"
+
+	# Lock Down
+	register "common_soc_config" = "{
+	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+	}"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on end # Host Bridge
+		device pci 01.0 on end # unused
+		device pci 01.1 on
+			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
+		end # PCIE Slot (JPCIE1)
+		device pci 04.0 on end # SA thermal subsystem
+		device pci 14.0 on end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on end # Thermal Subsystem
+		device pci 16.0 on end # Management Engine Interface 1
+		device pci 16.1 on end # Management Engine Interface 2
+		device pci 17.0 on end # SATA
+		device pci 1c.0 on
+			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
+		end # PCI Express Port 1 (Slot JPCIE1)
+		device pci 1c.2 on
+			device pci 00.0 on
+				device pci 00.0 on end # Aspeed 2400 VGA
+			end
+		end # PCI Express Port 3
+		device pci 1c.4 on
+			device pci 00.0 on end # 10GbE
+			device pci 00.1 on end # 10GbE
+		end # PCI Express Port 5
+		device pci 1d.0 on
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
+		end # PCI Express Port 9
+		device pci 1f.0 on
+			chip drivers/ipmi
+				# On cold boot it takes a while for the BMC to start the IPMI service
+				register "wait_for_bmc" = "1"
+				register "bmc_boot_timeout" = "60"
+				device pnp ca2.0 on end # IPMI KCS
+			end
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						device pnp 2e.2 on # SUART1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.3 on # SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.4 on # SWC
+							io 0x60 = 0xa00
+							io 0x62 = 0xa10
+							io 0x64 = 0xa20
+							io 0x66 = 0xa30
+							irq 0x70 = 0xb
+						end
+						device pnp 2e.5 on #  Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+							irq 0x72 = 0xc
+						end
+						device pnp 2e.7 on #  GPIO
+						end
+						device pnp 2e.b on #  SUART3
+							io 0x60 = 0x3e8
+							irq 0x70 = 4
+						end
+						device pnp 2e.c on # SUART4
+							io 0x60 = 0x2e8
+							irq 0x70 = 3
+						end
+						device pnp 2e.d on #  iLPC2AHB
+						end
+						device pnp 2e.e on #  Mailbox
+							io 0x60 = 0xa40
+							irq 0x70 = 0x00
+						end
+					end
+				end
+			end
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end # LPC Interface
+		device pci 1f.1 on end # P2SB
+		device pci 1f.2 on end # Power Management Controller
+		device pci 1f.4 on end # SMBus
+		device pci 1f.5 on end # SPI Controller
+	end
+end